RF Crosstalk Isolation

Portable electronics, data storage, and fast modems for internet access are the fastest
growing sectors of the microelectronics industry. Some of the key circuit components
for these applications include radio frequency (RF) power-amplifiers, intermediate
frequency (IF) mixers, and base-band circuitry that have conventionally been in GaAs,
Si bipolar, and Si CMOS technologies, respectively. The form factor, power consumption,
circuit design complexity, and cost will all improve if the various circuit components
are integrated on a single Si chip. One of the major challenges for single chip RFIC's is
RF crosstalk through the Si substrate. In other words, noise from switching transient in
digital circuits can be transmitted through the conducting Si substrate and degrade the
performance of analog circuit elements. Comparing to compound semiconductor technology,
the lacking of a semi-insulating state in Si material is probably the most challenging
technological hurdle in fabricating high performance RF integrated circuits especially
for passive components such as inductors. Capacitive and electromagnetic coupling between
on-chip inductors and the Si substrate limits the inductor performance and device design
freedom.

High performance SoC applications impose stringent requirement on the substrate. An ideal
substrate should be a good thermal conductor, provides good isolation for digital switching
noise (preferably < -100 dB) to ensure the proper operation of the noise sensitive RF circuits,
and allows for the integration of high performance on-chip inductors (Q>10). Typical
substrates for SoC applications include high resistivity Si and SOI, both rely on dielectric
insulation for RF isolation. However, the isolation performance of these approaches is far
from meeting the system requirement of -100 dB. As a result, high performance mixed-signal
systems such as cell phones and base stations employ separate chips for digital and analog
functions at the sacrifice of the overall cost.

On this subject, the research being carried out in our group aims at developing a
manufacturable technology of Si substrate impedance engineering for high performance
mixed-signal integrated circuit applications. The new technology consists of three key
elements: p-/p+ Si substrates in which the p+ substrate serves as a true ground plane;
metal via together with the p+ substrate to form Faraday cages for RF shielding as well as
providing true-ground contacts; and semi-insulating micro-porous Si moats of
through-the-wafer thickness inserted from the backside of the wafer to provide insulation
against noise and to serve as the foundation for on-chip inductors and bonding pads.
The engineered substrate consists of conducting as well as semi-insulating regions
strategically placed in 3-D throughout the volume of the substrate. On-chip inductors
are situated above the semi-insulating PS regions allowing for greatly increased Q-factor
and resonance frequency (fr). The only fabrication technique that is not used in the
conventional CMOS process flow is the electrochemical process that is scalable to batch
processing and has been proven to be manufacturable. These technologies require minimum
intrusion to conventional Si CMOS processing, making them practical and yet effective new
technologies that offer outstanding improvements with regard to the performance of
mixed-signal SoCs.

To date, we have experimentally demonstrated the superior performance achievable using the
3-D impedance engineering technology. RF crosstalk isolation of up to -50dB at 40 GHz has
been achieved and has been shown to be limited by the measurement setup. Simulation using
HFSS has shown the intrinsic performance could be as high as -100 dB at 40 GHz, a level that
has been beyond the reach of any known technology. On-chip inductors with Q~14 and fr~14GHz
and on-chip transformers with available power gain (Ga) of 0.77 at 5 GHz have been demonstrated.
Furthermore, bonding pads with superior crosstalk isolation and ultra-low capacitive coupling
to the substrate have also been demonstrated.

Both experimental measurements and theoretical simulation results point to the fact that
the 3-D impedance engineered substrate is the most promising technology to date for high
performance Si mixed-signal integrated circuit applications.



Semiconductor Materials Research Laboratory, Department of Materials Science and Engineering, University of California at Los Angeles
Box 951595, Los Angeles, CA 90095-1595 (Tel) +1 310 825 2971 UCLA SMRL © 2006 | All Rights Reserved