The first ASIC integrates control and interface circuitry for several basic I/O functions (keyboard, SCSI disks, LAN, etc.). I designed: the chip interface to the HP I/O bus, an internal I/O interrupt controller, and a 'watch-dog' timer for instrument control applications.
The second ASIC provides a bridge from the HP internal bus to the industry standard VME bus. On this project I designed: a programmable DMA controller and FIFO for mastered data transfers between VME and system memory, which included automatic byte alignment (for transfers that start and end at different byte offsets), data pre-fetching, and optimal VME cycle selection (including, if appropriate, VME D64 cycles); and a CPU-mastered ISA interface to support optional PCMCIA connection.
All designs were implemented using a combination of Verilog(TM) to describe the logic and Synopsys(TM) to generate gates, together with custom tools. My original contributions to this process included a custom tool to generate starting Verilog(TM) design and test modules from a simple state machine description, as well as a Verilog(TM) 'mirror' module for monitoring module state transitions. The mirror modules were used to check whether random top-level test vectors exercised all potential transitions for each state machine. I was also responsible for converting test simulations into functional vectors for chip manufacturing.