Brian Strope

bps@ucla.edu

An External Cache for the Motorola 68040

Before the PA-RISC-based HP700 series workstations, HP (like many other) workstations used Motorola processors (HP400 and 300 series). The MC68040 has highly-efficient, internal, physical, and independent data and instruction caches. However, when the processor requires data not currently cached, main memory DRAM latency can become a performance bottle-neck. I designed an optional 128K second-level cache to provide zero-wait state memory data, potentially sparing some of the DRAM latency penalty.

As a "high-performance" option, the external cache along with the memory and I/O interface controllers, connects directly to the MC68040 processor bus. The external cache is transparent in that it does not buffer or slow main memory accesses and maintains memory consistency through processor and alternate bus master (DMA) memory data transfers.

The design was implemented using discrete asynchronous SRAM, buffers, and control PALs.


home page
bps@ucla.edu