nanoDTL Publications, Presentations, and Patents


Publications
2014

  1. A. Pan and C. O. Chui, "RF Performance Limits of Ballistic Si Field-Effect Transistors," The IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Newport Beach, CA, January 20-22, 2014. (Invited Paper)
  2. S. Wang, A. Pan, C. O. Chui, and P. Gupta, "PROCEED: A Pareto Optimization-based Circuit-level Evaluator for Emerging Devices," The 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014) Proc., pp. 818-824, Singapore, January 20-23, 2014.
  3. K. Shoorideh and C. O. Chui, "On the Origin of Enhanced Sensitivity in Nanoscale FET-based Biosensors," Proc. Natl. Acad. Sci. USA, vol. 111, no. 14, pp. 5111-5116, 2014.
  4. L. Smith, G. Leung, J. Lau, B. Kolasa, R. Burkholder, M. Jack, B. Dunn, and C. O. Chui, "Scaled Carbon-Ionogel Supercapacitors for Electronic Circuits," presented in The IEEE National Aerospace and Electronics Conference (NAECON), Dayton, OH, June 25-27, 2014.
  5. A. Pan and C. O. Chui, "Modeling Direct Interband Tunneling. I. Bulk Semiconductors," J. Appl. Phys., vol. 116, art. 054508, 2014.
  6. A. Pan and C. O. Chui, "Modeling Direct Interband Tunneling. II. Lower-Dimensional Structures," J. Appl. Phys., vol. 116, art. 054509, 2014.
  7. Y. Yang, Y. Mao, C. O. Chui, and P.-Y. E. Chiou, "Self-Locking Optoelectronic Tweezers for Microparticle Manipulation across A Large Area," presented in The IEEE Int. Conf. Optical MEMS and Nanophotonics, Glasgow, Scotland, August 17-21, 2014.
  8. K. Shoorideh and C. O. Chui, "Understanding and Optimization of the Sensitivity of Nanoscale FET-Based Biosensors," presented in The SPIE Conference on Nanoepitaxy: Materials and Devices VI, San Diego, CA, August 17-21, 2014. (Invited Paper)
  9. Y. Mao, K.-S. Shin, F. Mashayekhi, L. Song, and C. O. Chui "Validation of Semiconductor Electronic Label-Free Assay (SELFA) for Point-of-Care Cardiac Troponin I Measurement," to be presented in The IEEE EMBS Special Topic Conference on Healthcare Innovation & Point-of-Care Technologies, Seattle, WA, October 8-10, 2014. (Late Breaking Research Paper)
  10. C. O. Chui, Y. Mao, and K.-S. Shin, "Semiconductor Electronic Label-Free Assay (SELFA)," to be presented in The 8th IEEE International Conference on Nano/Molecular Medicine and Engineering (IEEE-NANOMED 2014), Kaohsiung, Taiwan, November 9-12, 2014. (Invited Paper)

2013

  1. G. Leung and C. O. Chui, "Stochastic Variability in Silicon Double-Gate Lateral Tunnel Field-Effect Transistors," IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 84-91, 2013.
  2. S. M. Wen and C. O. Chui, "CMOS Junctionless FET Manufacturing Cost Evaluation," IEEE Trans. Semicond. Manuf., vol. 26, no. 1, pp. 162-168, 2013.
  3. P. Narayanan, M. Leuchtenburg, J. Kina, P. Joshi, P. Panchapakeshan, C. O. Chui, and C. A. Moritz, "Variability in Nanoscale Fabrics: Bottom-Up Integrated Analysis and Mitigation," ACM J. Emerg. Technol. Com. Syst., vol. 9, no. 1, art. 8, 2013.
  4. K.-H. Shih and C. O. Chui, "Analog/RF Performance and Optimization of Vertical III-V Double Gate Transistor," IEEE Trans. Electron Devices, vol. 60, no. 5, pp. 1613-1618, 2013.
  5. S. Wang, G. Leung, A. Pan, C. O. Chui, and P. Gupta, "Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies," IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2186-2193, 2013.
  6. K.-H. Shih, A. Pan, Y. Liu, and C. O. Chui, "A Systematic Approach for Hydrodynamic Model Calibration in the Quasi-Ballistic Regime," Solid-State Electronics, vol. 87, pp. 90-97, 2013.
  7. S. Khasanvis, M. Rahman, P. Shabadi, P. Narayanan, H. S. Yu, C. O. Chui, and C. A. Moritz, "Nanowire Field-Programmable Computing Platform," IEEE/ACM Int. Symp. Nanoscale Archit. (NANOARCH 2013), New York, NY, July 15-17, 2013.
  8. C. O. Chui, K.-S. Shin, and Y. Mao, "Ultrasensitive Biomolecular Assays with Amplifying Nanowire FET Biosensors," Proc. SPIE, vol. 8820, Nanoepitaxy: Materials and Devices V, 88200S (September 19, 2013); doi:10.1117/12.2026914. (Invited Paper)
  9. A. Pan, S. Chen, and C. O. Chui, "Electrostatic Modeling and Insights regarding Multigate Lateral Tunneling," IEEE Trans. Electron Devices, vol. 60, no. 9, pp. 2712-2720, 2013.
  10. G. Leung and C. O. Chui, "Interactions between Line Edge Roughness and Random Dopant Fluctuation in Non-Planar Field-Effect Transistor Variability," IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3277-3284, 2013.

2012

  1. L. Li, C. O. Chui, J. He, and M. Chan, "One-Time-Programmable Memory in LTPS TFT Technology with Metal Induced Lateral Crystallization," IEEE Trans. Electron Devices, vol. 59, no. 1, pp. 145-150, 2012.
  2. L. Li, L. Zhang, J. He, C. O. Chui, and M. Chan, "Phase-Change Memory with Multi-Fin Thin-Film-Transistor Driver Technology," IEEE Electron Device Lett., vol. 33, no. 3, pp. 405-407, 2012.
  3. K.-S. Shin, A. Pan, and C. O. Chui, "Channel Length Dependent Sensitivity of Schottky Contacted Silicon Nanowire Field-Effect Transistor Sensors," Appl. Phys. Lett., vol. 100, art. 123504, 2012.
  4. H. Rajagopalan, K.-S. Shin, J. Kina, C. O. Chui, and Y. Rahmat-Samii, "A Smart Diagnostic Capsule with a Novel Antenna and Nano-Biosensors," The 6th Eur. Conf. Antennas Propag. (EuCAP) Proc., pp. 190-193, Prague, Czech Republic, March 26-30, 2012. (Invited Paper)
  5. K.-S. Shin and C. O. Chui, "Nanomanufacturing Strategy for Aligned Assembly of Nanowire Arrays," J. Electron. Mater., vol. 41, no. 5, pp. 935-943, 2012.
  6. G. Leung and C. O. Chui, "Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs," IEEE Electron Device Lett., vol. 33, no. 6, pp. 767-769, 2012.
  7. P. Narayanan, J. Kina, P. Panchapakeshan, C. O. Chui, and C. A. Moritz, "Integrated Device-Fabric Explorations and Noise Mitigation in Nanoscale Fabrics," IEEE Trans. Nanotechnol., vol. 11, no. 4, pp. 687-700, 2012.
  8. G. Leung, L. Lai, P. Gupta, and C. O. Chui, "Device and Circuit Level Variability Caused by Line Edge Roughness for Sub-32nm FinFET Technologies," IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2057-2063, 2012.
  9. Y. Mao and C. O. Chui, "Transient Measurement Approaches to Differentiate Non-Specific Binding in Affinity-Based Bioanalytical Assays," J. Appl. Phys., vol. 112, art. 024702, 2012.
  10. C. O. Chui, K.-S. Shin, J. Kina, K.-H. Shih, P. Narayanan, and C. A. Moritz, "Heterogeneous Integration of Epitaxial Nanostructures - Strategies and Application Drivers," Proc. SPIE, vol. 8467, Nanoepitaxy: Materials and Devices IV, 84670R (October 11, 2012); doi:10.1117/12.970438. (Invited Paper)
  11. J. Zhang, P. Narayanan, S. Khasanvis, J. Kina, C. O. Chui, and C. A. Moritz, "On-Chip Variation Sensor for Systematic Variation Estimation in Nanoscale Fabrics," IEEE 12th Int. Conf. Nanotechnol. (IEEE NANO 2012) Dig., Birmingham, United Kingdom, August 20-23, 2012.
  12. A. Pan and C. O. Chui, "A Quasi-Analytical Model for Double-Gate Tunneling Field-Effect Transistors," IEEE Electron Device Lett., vol. 33, no. 10, pp. 1468-1470, 2012.
  13. K. Shoorideh and C. O. Chui, "Optimization of the Sensitivity of FET-Based Biosensors via Biasing and Surface Charge Engineering," IEEE Trans. Electron Devices, vol. 59, no. 11, pp. 3104-3110, 2012.

2011

  1. C. O. Chui, J. Kina, and K.-S. Shin, "3D Integrable Nanowire FET Sensor with Intrinsic Sensitivity Boost," The 2011 IEEE Int. Conf. on Integr. Circuit Design and Technol. (ICICDT) Tech. Dig., Paper B5, Kaohsiung, Taiwan, May 2-4, 2011. (Invited Paper)
  2. J. Kim, A. J. Hong, S. M. Kim, K.-S. Shin, E. B. Song, Y. Hwang, F. Xiu, K. Galatsis, C. O. Chui, R. N. Candler, S. Choi, J.-T. Moon, and K. L. Wang, "A Stacked Memory Device on Logic 3D Technology for Ultra-High-Density Data Storage," Nanotechnol., vol. 22, art. 254006, 2011.
  3. P. Narayanan, J. Kina, P. Panchapakeshan, P. Vijayakumar, K.-S. Shin, M. Rahman, M. Leuchtenburg, I. Koren, C. O. Chui, and C. A. Moritz, "Nanoscale Application Specific Integrated Circuits," IEEE/ACM Int. Symp. Nanoscale Archit. (NANOARCH 2011) Tech. Dig., pp. 99-106, San Diego, CA, June 8-9, 2011.
  4. K.-S. Shin and C. O. Chui, "Aligned Assembly of Nanowire Arrays with Intrinsic Control," TMS Electronic Mater. Conf. (EMC) Dig., Paper KK8, Santa Barbara, CA, June 22-24, 2011.
  5. P. Panchapakeshan, P. Vijayakumar, P. Narayanan, C. O. Chui, I. Koren, and C. A. Moritz, "3-D Integration Requirements for Hybrid Nanoscale-CMOS Fabrics," IEEE 11th Int. Conf. Nanotechnol. (IEEE NANO 2011) Dig., pp. 849-853, Portland, OR, August 15-18, 2011.
  6. P. Narayanan, P. Panchapakeshan, J. Kina, C. O. Chui, and C. A. Moritz, "Integrated Nanosystems with Junctionless Crossed Nanowire Transistors," IEEE 11th Int. Conf. Nanotechnol. (IEEE NANO 2011) Dig., pp. 845-848, Portland, OR, August 15-18, 2011.
  7. C. O. Chui and K.-S. Shin, "Integrated Amplifying Nanowire FET for Surface and Bulk Sensing," Proc. SPIE, vol. 8106, Nanoepitaxy: Materials and Devices III, 81060C (September 16, 2011); doi:10.1117/12.896476. (Invited Paper)
  8. G. Leung and C. O. Chui, "Variability of Inversion-Mode and Junctionless FinFETs due to Line Edge Roughness," IEEE Electron Device Lett., vol. 32, no. 11, pp. 1489-1491, 2011.

2010

  1. G. Leung and C. O. Chui, "Impact of Line Edge Roughness and Device Scaling on Double-Gate FinFET Variability," The 4th IEEE Int. Wrkshp. DFM&Y, Anaheim, CA, June 14, 2010.
  2. A. Pan, D.-S. Pan, and C. O. Chui, "Mechanism for Excess Noise in Mixed Tunneling and Avalanche Breakdown of Silicon," Appl. Phys. Lett., vol. 96, art. 263503, 2010.
  3. P. Narayanan, M. Leuchtenburg, J. Kina, P. Joshi, P. Panchapakeshan, C. O. Chui, and C. A. Moritz, "Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration," Proc. 25th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Syst. (DFT’10), pp. 24-31, Kyoto, Japan, October 6-8, 2010. (BEST STUDENT PAPER AWARD)
  4. C. O. Chui and K.-H. Shih, "High Mobility III-V Permeable Base Transistors with Suppressed Base Current," Proc. 218th Mtg. Electrochem. Soc., Paper E12-1768, Las Vegas, NV, October 10-15, 2010. (Invited Paper)
  5. K.-H. Shih and C. O. Chui, "High Mobility Compound Semiconductor Permeable Base Transistors with Suppressed Base Current," Electrochem. Soc. Trans., vol. 33, pp. 93-101, 2010.
  6. K.-S. Shin, K. Lee, J.-H. Park, J. Y. Kang, and C. O. Chui, "Schottky Contacted Nanowire Field-Effect Sensing Device with Intrinsic Amplification," IEEE Electron Device Lett., vol. 31, no. 11, pp. 1317-1319, 2010.

2009

  1. H. S. Yu and C. O. Chui, "Insights and Optimizations of Tunnel Field-Effect Transistor Operations," IEEE 67th Dev. Res. Conf. (DRC) Dig., Paper III-17, pp. 87-88, University Park, PA, June 22-24, 2009.
  2. P. Narayanan, K. W. Park, C. O. Chui, and C. A. Moritz, "Manufacturing Pathway and Associated Challenges for Nanoscale Computational Systems," IEEE 9th Int. Conf. Nanotechnol. (IEEE NANO 2009) Dig., Genoa, Italy, July 26-30, 2009.
  3. P. Narayanan, C. A. Moritz, K. W. Park, and C. O. Chui, "Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration," IEEE/ACM Int. Symp. Nanoscale Archit. (NANOARCH 2009) Tech. Dig., pp. 37-42, San Francisco, CA, July 30-31, 2009. (Best Paper Award Finalist)
  4. K.-S. Shin, K. Lee, J. Y. Kang, and C. O. Chui, "Novel T-Channel Nanowire FET with Built-in Signal Amplification for pH Sensing," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 26.3, pp. 599-602, Baltimore, MD, December 7-9, 2009.

2008

  1. K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. C. Saraswat, H. E. Maes, and G. Groeseneken, "On the Correct Extraction of Interface Trap Density of MOS Devices with High-Mobility Semiconductor Substrates," IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 547-556, 2008.
  2. P. T. Chen, Y. Sun, E. Kim, P. C. McIntyre, W. Tsai, M. Garner, P. Pianetta, Y. Nishi, and C. O. Chui, "HfO2 Gate Dielectric on (NH4)2S Passivated (100) GaAs Grown by Atomic Layer Deposition," J. Appl. Phys., vol. 103, art. 034106, 2008.
  3. K.-H. Shih and C. O. Chui, "The Low Subthreshold Swing Possibility with Asymmetries in Double-Gate SOI MOSFET," Proc. 2008 IEEE Int. SOI Conf., pp. 53-54, New Paltz, NY, October 6-9, 2008.
  4. C. O. Chui, K.-H. Shih, and K. Shoorideh, "Low Dissipation Nanoscale Transistor Physics and Operations," Proc. 9th Int. Conf. on Solid-State and Integr. Circuit Technol. (ICSICT), Paper A1.3, pp. 29-32, Beijing, People's Republic of China, October 20-23, 2008. (Invited Paper)

2007

  1. E. Kim, J. Chen, D. Choi, N. Goel, C. O. Chui, W. Tsai, J. Harris, Y. Nishi, K. Saraswat, and P. C. McIntyre, "Electrical and Physical Characterization of ALD-Grown HfO2 Gate Dielectrics on GaAs (100) Substates with Sulfur Passivation," Proc. 2007 Mater. Res. Soc. Spr. Mtg., Symp. Extending Moore's Law with Advanced Channel Materials, Paper G5.12, San Francisco, CA, April 9-13, 2007.
  2. P.-T. J. Chen, Y. Sun, C. O. Chui, E. Kim, M. Garner, P. Pianetta, N. Goel, W. Tsai, P. McIntyre, and Y. Nishi, "Interface Analysis Between ALD High-k HfO2 and Sulfur Passivated GaAs," Proc. 2007 Mater. Res. Soc. Spr. Mtg., Symp. High-k Interfaces: High Mobility Substrates and Metal Electrodes, Paper H4.3, San Francisco, CA, April 9-13, 2007.
  3. D. Choi, M. Warusawithana, C. O. Chui, N. Goel, W. Tsai, D. G. Schlom, and J. S. Harris, "Surface Reconstruction Dependence and Annealing of Amorphous Lanthanum Aluminate on GaAs," Proc. 2007 Mater. Res. Soc. Spr. Mtg., Symp. High-k Dielectrics/Semiconductor Interfaces, Paper H5.31, San Francisco, CA, April 9-13, 2007.
  4. D. Choi, M. Warusawithana, C. O. Chui, J. Chen, W. Tsai, D. G. Schlom, and J. S. Harris, "The Electrical Characterization of Molecular-Beam-Deposited LaAlO3 on GaAs and Its Annealing Effects," Mater. Res. Soc. Symp. Proc., vol. 996, Paper H5.31, 2007.
  5. C. O. Chui, "High Mobility Nanoelectronic Devices, Physics, and Technology," Proc. 7th Int. Symp. Adv. Fluid Inf. and 4th Int. Symp. Transdiscipl. Fluid Integrat., pp. 84-91, Institute of Fluid Science, Tohoku University, Sendai, Japan, December 15, 2007. (Keynote Lecture)

2006

  1. K. C. Saraswat, C. O. Chui, P. Kapur, T. Krishnamohan, A. Nayfeh, A. K. Okyay, and R. S. Shenoy, "Performance Limitations of Si CMOS and Alternatives for Nanoelectronics," Int. J. of High-Speed Electronics and Syst., vol. 16, no. 1, pp. 175-192, 2006. (Invited Paper)
  2. A. K. Okyay, C. O. Chui, and K. C. Sarawat, "Leakage Suppression by Asymmetric Area Electrodes in Metal-Semiconductor-Metal Photodetectors," Appl. Phys. Lett., vol. 88, art. 063506, 2006.
  3. C. O. Chui, F. Ito, and K. C. Saraswat, "Nanoscale Germanium MOS Dielectrics―Part I: Germanium Oxynitrides," IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1501-1508, 2006. (Review Paper)
  4. C. O. Chui, H. Kim, D. Chi, P. C. McIntyre, and K. C. Saraswat, "Nanoscale Germanium MOS Dielectrics―Part II: High-k Gate Dielectrics," IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1509-1516, 2006. (Review Paper)
  5. H. Lan, T. W. Chen, C. O. Chui, P. Nikaeen, J. W. Kim, and R. W. Dutton, "Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs," IEEE J. of Solid-State Circuits (Special Issue on the IEEE 2005 Custom Integr. Circuit Conf.), vol. 41, no. 8, pp. 1817-1829, 2006.
  6. N. Goel, P. Majhi, C. O. Chui, W. Tsai, D. Choi, and J. S. Harris, "InGaAs Metal-Oxide-Semiconductor Capacitors with HfO2 Gate Dielectric Grown by Atomic-Layer Deposition," Appl. Phys. Lett., vol. 89, art. 163517, 2006.
  7. P. C. McIntyre, D. Chi, C. O. Chui, H. Kim, K. I. Seo, and K. C. Saraswat, "Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?" Proc. 210th Mtg. Electrochem. Soc., Paper E13-1456, Cancun, Mexico, October 29-November 3, 2006. (Invited Paper)
  8. P. C. McIntyre, D. Chi, C. O. Chui, H. Kim, K.-I. Seo, K. C. Saraswat, R. Sreenivasan, T. Sugawara, F. S. Aguirre-Testado, and R. M. Wallace, "Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?" Electrochem. Soc. Trans., vol. 3, no. 7, pp. 519-530, 2006. (Invited Paper)
  9. K. C. Saraswat, C. O. Chui, D. Kim, T. Krishnamohan, and A. Pethe, "High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 25.2, pp. 659-662, San Francisco, CA, December 11-13, 2006. (Invited Paper)
  10. K. C. Saraswat, C. O. Chui, T. Krishnamohan, D. Kim, A. Nayfeh, and A. Pethe, "High Performance Germanium MOSFETs," Mater. Sci. Eng. B, vol. 135, no. 3, pp. 242-249, 2006. (Invited Paper)
  11. T. J. Grassman, S. R. Bishop, A. C. Kummel, C. O. Chui, and W. Tsai, "Comparison of ZrO2/Ge(100) and HfO2/Ge(100) Bonding and Electronic Structure," The 37th IEEE Semicond. Interface Specialists Conf. (SISC) Techn. Dig., San Diego, CA, December 7-9, 2006.

2005 and Before

  1. T.-Y. Chiang, S. J. Souri, C. O. Chui, and K. C. Saraswat, "Thermal Analysis of Heterogeneous 3-D ICs with Various Integration Scenarios," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 31.2, pp. 681-684, Washington, DC, December 2-5, 2001.
  2. C. O. Chui and K. C. Saraswat, "Germanium Damascene Process by Selective LPCVD and Surface Smoothening Technique," Proc. 2002 Mater. Res. Soc. Spr. Mtg., Symp. Growth: New Methods and Fundamentals, Paper A19.5, San Francisco, CA, April 1-5, 2002.
  3. C. O. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "Ultrathin High-k Gate Dielectric Technology for Germanium MOS Applications," IEEE 60th Annual Dev. Res. Conf. (DRC) Dig., Paper VII.B-2, pp. 191-192, Santa Barbara, CA, June 24-26, 2002. (BEST STUDENT PAPER AWARD)
  4. C. O. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "Germanium MOS Capacitors Incorporating Ultrathin High-k Gate Dielectric," IEEE Electron Device Lett., vol. 23, no. 8, pp. 473-475, 2002.
  5. C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A Sub-400ºC Germanium MOSFET Technology with High-k Dielectric and Metal Gate," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 17.3, pp. 437-440, San Francisco, CA, December 8-11, 2002.
  6. H. Kim, P. C. McIntyre, C. O. Chui, and K. C. Saraswat, "Atomic Layer Deposition of ZrO2 on Si and Ge Substrate," Proc. 2003 Mater. Res. Soc. Spr. Mtg., Symp. High-k Dielectrics, Paper D2.11, San Francisco, CA, April 21-25, 2003.
  7. D. Chi, B. B. Triplett, P. C. McIntyre, C. O. Chui, K. C. Saraswat, E. Garfunkel, and T. Gustafsson, "High-k Metal Oxides Dielectrics on Ge (100) Substrates," Proc. 2003 Mater. Res. Soc. Spr. Mtg., Symp. Advanced Gate Stack Materials, Paper D3.17, San Francisco, CA, April 21-25, 2003.
  8. K. C. Saraswat, C. O. Chui, P. C. McIntyre, and B. B. Triplett, "Novel Germanium Technology and Devices for High Performance MOSFETs and Integrated On-Chip Optical Clocking," Proc. 203rd Mtg. Electrochem. Soc., Paper G1-455, Paris, France, April 27-May 2, 2003. (Invited Paper)
  9. A. K. Okyay, C. O. Chui, and K. C. Saraswat, "Asymmetric Group IV MSM Photodetectors with Reduced Dark Currents," IEEE Conf. Lasers and Electro-Optics (CLEO) Tech. Dig., Paper CTuD4, pp. 464-466, Baltimore, MD, June 3-5, 2003.
  10. D. Chi, C. O. Chui, S. Ramanathan, B. B. Triplett, K. C. Saraswat, and P. C. McIntyre, "UV-Ozone Oxidized High-k Dielectrics on Si and Ge Substrates," The 45th TMS Electronic Mater. Conf. (EMC) Dig., Paper S5, Salt Lake City, UT, June 25-27, 2003.
  11. H. Kim, C. O. Chui, K. C. Saraswat, and P. C. McIntyre, "Local Epitaxial Growth of ZrO2 on Ge (100) Substrates by Atomic Layer Epitaxy," Appl. Phys. Lett., vol. 83, no. 13, pp. 2647-2649, 2003.
  12. C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, "Activation and Diffusion Studies of Ion-Implanted p and n Dopants in Germanium," Appl. Phys. Lett., vol. 83, no. 16, pp. 3275-3277, 2003.
  13. C. O. Chui, A. K. Okyay, and K. C. Saraswat, "Effective Dark Current Suppression with Asymmetric MSM Photodetectors in Group IV Semiconductors," IEEE Photon. Technol. Lett., vol. 15, no. 11, pp. 1585-1587, 2003.
  14. C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, "A Germanium NMOSFET Process Integrating Metal Gate and Improved Hi-k Dielectrics," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 18.3, pp. 437-440, Washington, DC, December 7-10, 2003.
  15. C. O. Chui, H. Kim, J. P. McVittie, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A Novel Self-Aligned Gate-Last MOSFET Process Comparing the High-k Candidates," IEEE 2003 Int. Semicond. Dev. Res. Symp. (ISDRS) Proc., Paper FA6-05, pp. 464-465, Washington, DC, December 10-12, 2003.
  16. P. McIntyre, H. Kim, D. Chi, C. O. Chui, B. Triplett, A. Javey, H. Dai, and K. Saraswat, "Novel Deposition Processes for High-k/Ge Devices: Interface Engineering," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-k and High Mobility Substrates, Paper B5.1/D5.1, San Francisco, CA, April 12-16, 2004. (Invited Paper)
  17. C. O. Chui, D.-I. Lee, A. A. Singh, D. Chi, P. C. McIntyre, P. A. Pianetta, and K. C. Saraswat, "Synchrotron Radiation Photoemission Spectroscopy of High-k Gate Stack in High-Performance Ge MOS Devices," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-k and High Mobility Substrates, Paper B5.2/D5.2, San Francisco, CA, April 12-16, 2004.
  18. D. Chi, C. O. Chui, S. Ramanathan, B. Triplett, K. C. Saraswat, and P. C. McIntyre, "Metal Oxide/Semiconductor Interfaces in UV-Ozone Oxidized High-k Dielectric Stacks on Si and Ge (001) Substrates," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-k and High Mobility Substrates, Paper B5.6/D5.6, San Francisco, CA, April 12-16, 2004.
  19. C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, "Ge MOS Dielectric Stack with ALD High-k Metal Oxide and Oxynitride Interlayer," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-Mobility Group-IV Mat. Dev., Paper B8.7, San Francisco, CA, April 12-16, 2004.
  20. H. Kim, P. C. McIntyre, S. Stemmer, C. O. Chui, and K. C. Saraswat, "High-k Interface Engineering: the Interaction of Reactive Metal Electrodes with ALD-ZrO2/SiO2 and HfO2/SiO2 Gate Stacks," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. Metal Gates, Paper D4.4, San Francisco, CA, April 12-16, 2004.
  21. C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, "Atomic Layer Deposition of High-k Dielectric for Germanium MOS Applications―Substrate Surface Preparation," IEEE Electron Device Lett., vol. 25, no. 5, pp. 274-276, 2004.
  22. C. O. Chui and K. C. Saraswat, "Low Thermal Budget Ge MOS Technology," Proc. 205th Mtg. of Electrochem. Soc., Paper G1-254, San Antonio, TX, May 9-14, 2004. (Invited Paper)
  23. C. O. Chui and K. C. Saraswat, "Advanced Germanium MOSFET Technologies with High-k Gate Dielectrics and Shallow Junctions," The 2004 IEEE Int. Conf. on Integr. Circuit Design and Technol. (ICICDT) Tech. Dig., Paper H2, pp. 245-252, Austin, TX, May 17-19, 2004. (Invited Paper)
  24. H. Kim, P. C. McIntyre, C. O. Chui, K. Saraswat, and S. Stemmer, "Engineering Chemically Abrupt High-k Metal Oxide/Silicon Interfaces Using Oxygen-Gettering Metal Overlayers," The 13th Wrkshp. Dielectrics in Microelectronics (WoDiM 2004), Paper 4a-2, Kinsale, Ireland, June 28-30, 2004. (BEST PAPER AWARD)
  25. D. Chi, C. O. Chui, K. C. Saraswat, B. B. Triplett, and P. C. McIntyre, "Zirconia Grown by Ultraviolet Ozone Oxidation on Germanium (100) Substrates," J. Appl. Phys., vol. 96, no. 1, pp. 813-819, 2004.
  26. M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, "Integration of Optical Polymer Pillars Chip I/O Interconnections with Si MSM Photodetectors," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1084-1090, 2004.
  27. C. O. Chui, F. Ito, and K. C. Saraswat, "Scalability and Electrical Properties of Germanium Oxynitride MOS Dielectrics," IEEE Electron Device Lett., vol. 25, no. 9, pp. 613-615, 2004.
  28. H. Kim, P. C. McIntyre, C. O. Chui, K. C. Saraswat, and S. Stemmer, "Engineering Chemically Abrupt High-k Metal Oxide/Silicon Interfaces Using An Oxygen-Gettering Metal Overlayer," J. Appl. Phys., vol. 96, no. 6, pp. 3467-3472, 2004.
  29. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. K. Okyay, H. Kim, and P. McIntyre, "Ge and SiGe for High Performance MOSFETs and Integrated Optical Interconnects," The 2004 Int. Conf. on Solid State Dev. Mater. (SSDM) Tech. Dig., Tokyo, Japan, September 14-17, 2004. (Invited Paper)
  30. A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Effects of Hydrogen Annealing on Heteroepitaxial-Ge Layers on Si: Surface Roughness and Electrical Quality," Appl. Phys. Lett., vol. 85, no. 14, pp. 2815-2817, 2004.
  31. H. Kim, P. C. McIntyre, C. O. Chui, K. C. Saraswat, and M.-H. Cho, "Interfacial Characteristics of HfO2 Grown on Nitrided Ge (100) Substrates by Atomic-Layer Deposition," Appl. Phys. Lett., vol. 85, no. 14, pp. 2902-2904, 2004.
  32. A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Effects of Hydrogen Annealing on Heteroepitaxial-Ge Layers on Si: Surface Roughness and Electrical Quality," Proc. 206th Mtg. Electrochem. Soc., Paper M2-1403, Honolulu, HI, October 3-8, 2004.
  33. H. Lan, T. W. Chen, C. O. Chui, and R. W. Dutton, "Compact Modeling and Experimental Verification of Substrate Resistance in Lightly Doped Substrates," Proc. 12th Wrkshp. on Syn. and Syst. Integrat. of Mixed Inf. Technol. (SASIMI), pp. 189-195, Kanazawa, Japan, October 18-19, 2004.
  34. K. C. Saraswat, C. O. Chui, A. Nayfeh, H. Kim, and P. McIntyre, "Ge Surface Passivation for High Performance MOSFETs," The 35th IEEE Semicond. Interface Specialists Conf. (SISC) Tech. Dig., San Diego, CA, December 9-11, 2004. (Invited Paper)
  35. E. Pop, C. O. Chui, S. Sinha, R. Dutton, and K. Goodson, "Electro-Thermal Comparison and Performance Optimization of Thin-Body SOI and GOI MOSFETs," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 16.6, pp. 411-414, San Francisco, CA, December 13-15, 2004.
  36. K. C. Saraswat, C. O. Chui, P. Kapur, T. Krishnamohan, A. Nayfeh, A. K. Okyay, and R. S. Shenoy, "Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics," Proc. 2004 Adv. Wrkshp. on ‘Frontiers in Electronics’ (WOFE), Palm Beach, Aruba, December 18-22, 2004. (Invited Paper)
  37. P. C. McIntyre, H. Kim, K.-I. Seo, C. O. Chui, B. B. Triplett, D.-I. Lee, P. Pianetta, S. Stemmer, and K. C. Saraswat, "Interface Engineering for High-k/Si and High-k/Ge Structures," Proc. 10th Wrkshp. on Formation, Characterization and Reliability of Ultrathin Silicon Oxides, Mishima, Japan, January 28-29, 2005. (Invited Paper)
  38. K. C. Saraswat, C. O. Chui, A. Nayfeh, H. Kim, A. K. Okyay, and P. C. McIntyre, "Ge Based High Performance Nanoscale MOSFETs and Integrated Optical Interconnects," SEMICON Korea, Seoul, South Korea, February 2-4, 2005. (Invited Paper)
  39. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and R. S. Shenoy, "Performance Limitations of Si CMOS and Alternatives for Nanoelectronics," SEMI-ECS 2005 Int. Semicond. Technol. Conf. (ISTC), Shanghai, People's Republic of China, March 15-17, 2005. (Invited Paper)
  40. C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat, "A Reason for Poor Ge n-MOSFET Performance: Source/Drain Junction Dose-Dependent Activation," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Transistor Processing and Characterization-I, Paper G7.3, San Francisco, CA, March 28-April 1, 2005.
  41. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge Based High Performance Nanoscale MOSFETs," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Transistor Processing and Characterization-II, Paper G14.1, San Francisco, CA, March 28-April 1, 2005. (Invited Paper)
  42. A. K. Okyay, C. O. Chui, M. S. Bakir, J. D. Meindl, and K. C. Saraswat, "Integration of Polymer Pillar Optical Interconnects with Group IV MSM Photodetectors," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Photonic Systems, Paper D4.1, San Francisco, CA, March 28-April 1, 2005.
  43. A. M. Nayfeh, C. O. Chui, T. Yonehara, and K. Saraswat, "High Quality Heteroepitaxial-Ge Layers on Si by Multi-Step Hydrogen Annealing and Re-Growth," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Physical and Electrical Characterization-I, Paper G8.4, San Francisco, CA, March 28-April 1, 2005.
  44. A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, "Fabrication of High-Quality p-MOSFET in Ge Grown Heteroepitaxially on Si," IEEE Electron Device Lett., vol. 26, no. 5, pp. 311-313, 2005.
  45. C. O. Chui, D.-I. Lee, A. A. Singh, P. A. Pianetta, and K. C. Saraswat, "Zirconia-Germanium Interface Photoemission Spectroscopy Using Synchrotron Radiation," J. Appl. Phys., vol. 97, art. 113518, 2005.
  46. A. K. Okyay, C. O. Chui, and K. C. Saraswat, "A Novel Technique to Reduce Leakage in Metal-Semiconductor-Metal Photodetectors," IEEE 63rd Annual Dev. Res. Conf. (DRC) Dig., Paper III-8, pp. 69-70, Santa Barbara, CA, June 20-22, 2005.
  47. A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, "High Mobility Ge pMOS Fabricated Using a Novel Heteroepitaxial Ge on Si Growth Method," IEEE 63rd Annual Dev. Res. Conf. (DRC) Dig., Paper III-18, pp. 89-90, Santa Barbara, CA, June 20-22, 2005.
  48. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge Based High Performance Nanoscale MOSFETs," The 14th Bi-annual Conf. on Insulating Films on Semicond. (INFOS), Leuven, Belgium, June 22-24, 2005. (Invited Paper)
  49. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge Based High Performance Nanoscale MOSFETs," Microelectron. Eng., vol. 80, pp. 15-21, 2005. (Invited Paper)
  50. C.-H. Lu, G. M. T. Wong, M. D. Deal, W. Tsai, P. Majhi, C. O. Chui, M. R. Visokay, J. J. Chambers, L. Colombo, B. M. Clemens, and Y. Nishi, "Characteristics and Mechanism of Tunable Work Function Gate Electrodes Using a Bilayer Metal Structure on SiO2 and HfO2," IEEE Electron Device Lett., vol. 26, no. 7, pp. 445-447, 2005.
  51. C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat, "Germanium n-Type Shallow Junction Activation Dependences," Appl. Phys. Lett., vol. 87, art. 091909, 2005.
  52. H. Lan, T. W. Chen, C. O. Chui, P. Nikaeen, J. W. Kim, and R. W. Dutton, "Synthesized Compact Model and Experimental Results for Substrate Noise Coupling in Lightly Doped Processes," Proc. IEEE Custom Integr. Circuit Conf. (CICC), Paper 13-4, pp. 469-472, San Jose, CA, September 18-21, 2005.
  53. K. C. Saraswat, A. Nayfeh, and C. O. Chui, "Gate Dielectrics for Ge MOS Technology," Proc. 208th Mtg. Electrochem. Soc., Paper G3-0489, Los Angeles, CA, October 16-21, 2005. (Invited Paper)
  54. K. Shin, C. O. Chui, and T.-J. King, "Dual Stress Capping Layer Enhancement Study for Hybrid Orientation FinFET CMOS Technology," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 39.6, pp. 1009-1012, Washington, DC, December 5-7, 2005.
  55. C. O. Chui and K. C. Saraswat, "Advanced Germanium MOS Devices and Technology," The 2005 IEEE Int. Conf. on Electron Dev. and Solid-State Circuits (EDSSC) Tech. Dig., pp. 101-106, Hong Kong, People's Republic of China, December 19-21, 2005. (Invited Paper)

Book Chapters

     1.     K. C. Saraswat, C. O. Chui, P. Kapur, T. Krishnamohan, A. Nayfeh, A. K. Okyay, and R. S. Shenoy, "Performance Limitations of Si CMOS and Alternatives for Nanoelectronics," Frontiers in Electronics: Proceedings of the WOFE-04 (edited by H. Iwai, Y. Nishi, M. S. Shur, and H. Wong), World Scientific, New Jersey, Aug 2006.
     2.     C. O. Chui and K. C. Saraswat, "Nanoscale Germanium MOS Dielectrics and Junctions," Germanium-Based Technologies: From Materials to Devices (edited by C. Claeys and E. Simoen), Elsevier Science, Amsterdam, May 2007.
     3.     C. O. Chui and K. C. Saraswat, "Advances Germanium MOS Devices," Germanium-Based Technologies: From Materials to Devices (edited by C. Claeys and E. Simoen), Elsevier Science, Amsterdam, May 2007.
     4.     C. O. Chui and K. C. Saraswat, "Germanium Nanodevices and Technology," Advanced Gate Stacks for High-Mobility Semiconductors (edited by A. Dimoulas, E. Gusev, P. McIntyre, and M. Heyns), Springer-Verlag, New York, December 2007.
     5.     C. A. Moritz, P. Narayanan, and C. O. Chui, "Nanoscale Application Specific Integrated Circuits," Nanoelectronic Circuit Design (edited by N. K. Jha and D. Chen), Springer, New York, January 2011.
     6.     G. Leung and C. O. Chui, "Variability in Nanoscale FinFET Technologies," Toward Quantum FinFET (edited by W. Han and Z. M. Wang), Springer, New York, December 2013.

Issued Patents

  1. C. O. Chui, K. C. Saraswat, B. B. Triplett, and P. C. McIntyre, "High-k Dielectric for Thermodynamically-Stable Substrate-Type Materials," US Patent No. 7,271,458, issued on September 18, 2007.
  2. C. O. Chui, P. Majhi, W. Tsai, and J. T. Kavalieros, "Forming a Type I Heterostructure in a Group IV Semiconductor," US Patent No. 7,435,987, issued on October 14, 2008.
  3. A. M. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Germanium Substrate-Type Materials and Approach Therefor," US Patent No. 7,495,313, issued on February 24, 2009.
  4. C. O. Chui, P. Majhi, W. Tsai, and J. T. Kavalieros, "Strain-Inducing Semiconductor Regions," US Patent No. 7,629,603, issued on December 8, 2009.
  5. A. M. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Germanium Substrate-Type Materials and Approach Therefor," US Patent No. 7,772,078, issued on August 10, 2010.
  6. A. M. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Germanium Substrate-Type Materials and Approach Therefor," US Patent No. 7,919,381, issued on April 5, 2011.
  7. C. O. Chui, P. Majhi, W. Tsai, and J. T. Kavalieros, "Forming a Non-Planar Transistor Having a Quantum Well Channel," US Patent No. 7,928,426, issued on April 19, 2011.
  8. C. O. Chui, P. Majhi, W. Tsai, and J. T. Kavalieros, "Forming a Non-Planar Transistor Having a Quantum Well Channel," US Patent No. 8,237,153, issued on August 7, 2012.