Dynamics of Misfit Dislocation Formation in p/p+ Vapor Phase Epitaxy
P. Feichtinger, H. Fukuto, M.S. Goorsky, Dept of Materials Science and Engineering, University of California, Los Angeles; D. Oster, M. Rao, and J. Moreland, Wacker Siltronic Corporation, Portland, OR.
Edge polishing and other edge treatments are becoming important for large diameter silicon wafers. We examined the influence of wafer edge treatments on the evolution of misfit dislocations in p/p+ silicon wafers. Elimination of misfit dislocations is very important for the successful fabrication of high quality electronic devices. We investigated the origin and glide activation energies of misfit dislocations in p/p+ silicon wafers. The samples were 150 mm Czochralski grown wafers. Different edge treatments were used during the processing of the wafers to create a variation of edge shape and roughness. Nominally boron doped epitaxial layers beyond the critical thickness were deposited by vapor phase epitaxy at 1050 – 1100°C in a single wafer reactor. The misfit dislocation propagation velocity as a function of stress in the epitaxial layers was measured using post-growth thermal treatments of wafers with different levels of stress. The influence of the wafer shape and roughness on the observed misfit dislocation segments was studied. Double crystal x-ray topography was used to visualize the length of the misfit dislocation segments around the wafer periphery. Various misfit segment lengths were observed within one sample. This distribution of misfit dislocation length suggests more than one misfit dislocation nucleation event. In regions where the misfit dislocations were located, triple axis x-ray diffraction measurements were performed to determine the amount of layer relaxation. Misfit segments around the wafer periphery were observed at the interface after removal of the epitaxial layer by Secco etching. Densities were counted using standard optical microscope with a Nomarski setup. All results suggest that a potential misfit nucleation source is crystalline roughness at the wafer periphery.