Prior to my current role at SambaNova, I spent five years at Google designing five Tensor Processing Unit (TPU) chips for the datacenter, starting with the v4/v4i family. My most recent role there was as memory system technical lead for a cross-functional team of more than 15 hardware engineers.

My contributions to the TPU spanned most of the subsystems, although most of my impact was on the memory system, host interface, and inter-chip interconnect architecture and microarchitecture. Together with a colleague, I also landed an internal Chip Development Kit (CDK) from scratch. It is a set of comprehensively specified, parameterizable, and formally verified RTL libraries that implement common dataflow primitives with high performance and minimal area. They have been used to improve the development velocity of several different Google chips (not just TPUs) using a correct-by-construction approach.

I received my Ph.D. in Electrical Engineering from UCLA in Spring 2017. The topic of my dissertation was "Opportunistic Memory Systems in Presence of Hardware Variability." My research focused on a broad set of problems in computer architecture, VLSI design, and system software, focusing on memory variability and reliability.

In 2016, I won the Qualcomm Innovation Fellowship and the UCLA Dissertation Year Fellowship for my work on "Software-Defined Error-Correcting Codes."

When not working, you can usually find me enjoying life with my wonderful spouse, cat, friends, and family. I am a motorsports addict and I am often at a local racetrack or simracing online.

Learning and sharing knowledge with others is deeply fulfilling.