|   Puneet Gupta
My research interests primarily lie in CAD for VLSI physical design and
An overview of my main
research works is as follows.
Analysis of Manufacturing Variability
We proposed a new framework for assessing the impact of process
variation on circuit performance and product value with respect to
such relevant metrics as parametric yield at selling point,
and amount of required design guardbanding. We also evaluate
the merits of taking into account such previously unconsidered
phenomena as correlations among process parameters. Our results
indicate that the impact of variability is decreasing as technology
scales. We also proposed the concept of Design for Value to explicitly aim at maximizing a $/wafer metric in circuit optimization.
- Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, ``Design Sensitivities to Variability:
Extrapolation and Assessments in Nanometer VLSI'', IEEE ASIC/SoC Conference, September 2002, pp. 411-415.
Reducing Cost of Lithographic Correction
RET insertion and the resulting photomask complexity is becoming a major
cost of design, especially for low-volume ASICs. RETs such as optical
proximity correction (OPC) are oblivious of designer's intent and
design function (e.g., timing criticalities, sensitivities, etc.);
this results in unnecessary and costly overcorrection.
We have proposed a novel minimum cost of correction
(MinCorr) methodology to determine the minimum level of correction
for each layout feature subject to the constraint that
prescribed parametric yield is attained.
We highlight potential solutions to the
MinCorr problem and conclude that it is
possible to reduce the total cost of OPC significantly while still meeting yield
and cycle time targets by making OPC design aware. In a followup work with Photronics, we see such a technique getting 30% mask write time reduction on a real mask writer.
Separately, during the course of my internship at IBM T.J. Watson
Research Center, we proposed a new library-based OPC flow which can
save orders of magnitude in OPC runtime as well as make impact of OPC
predictable during design. The results suggest almost no loss of CD
control compared to traditional full-chip OPC.
- D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang,
``Toward performance-driven reduction of the cost of RET-based
lithography control'' (Invited Paper), Proc. SPIE Conf. on
Design and Process Integration for Microelectronic Manufacturing,
Feb 2003, to appear.
- P. Gupta, A. B. Kahng, D. Sylvester and J. Yang,
``A Cost-Driven Lithographic Correction Methodology Based on
Off-the-Shelf Sizing Tools'', Design Automation Conference,
2003, pp. 16-21.
- P. Gupta, F.-L. Heng, M. Lavin, ``Merits of Cellwise
Model-Based OPC'', Proc. SPIE Conf. on Design and Process
Integration for Microelectronic Manufacturing, Feb 2004, to appear.
- Y. Zhang, R. Gray, O.S. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler ``Interaction and balance of mask write time and design RET strategies'' Proc. SPIE Photomask Japan, 2005.
- P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, ``Performance-Driven OPC for Mask Cost Reduction'', Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 270-275.
- P. Gupta, A.B. Kahng, S. Muddu, O.S. Nakagawa, C.-H. Park, ``Modeling OPC Complexity for Design for Manufacturability'', Proc. 25th BACUS Symposium on Photomask Technology and Management, October 2005.
Performance-Aware Fill Insertion
Dummy fill insertion, post-tapeout, is a standard practice to improve
uniformity of chemical-mechanical planarization steps in wafer processing.
The timing impact of dummy fill is typically worst-cased during
physical design, or else ignored altogether. Dummy fill insertion
is completely unaware of the design, and current methods at best rely
on simple rules to limit capacitance impact. We review and develop
estimates for capacitance and timing overhead of area fill insertion.
We then give the first formulation of the performance impact limited
fill (PIL-Fill) insertion problem. We propose ILP formulations as well
as heuristics to solve the PIL-Fill problem. Our results indicate
significant improvements in post-fill timing without loss in layout
density control. We are currently improving the proposed algorithms to
account for multi-layer effects.
- Y. Chen, P. Gupta, and A. B. Kahng, ``Performance-Impact Limited Dummy Fill Insertion'',
Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb 2003, to appear.
- Y. Chen, P. Gupta and A. B. Kahng, ``Performance-Impact Limited Area Fill Synthesis'',
Design Automation Conference, 2003, pp. 16-21.
Scan Chain Synthesis
Scan chain insertion can have a large impact on routability,
wirelength and timing of the design. We have proposed a routing-based
scan chain ordering flow which achieves up to 80% reduction in wirelength
impact compared to the traditional placement-based approach. We have
extended this work to achieve timing-feasible scan insertion wherein
we find the minimum-wirelength timing-feasible connection point for
a scan connection. In a related work, we have investigated scan chain
ordering for improved, layout-aware delay fault coverage.
We propose a multi-fragment greedy algorithm that solves the associated
asymmetric traveling salesman problem in a manner that permits exploration
of the tradeoff between test coverage and layout impact. We see up to 200%
improvement in delay fault coverage with just 20% increase in wirelength
compared to layout-driven scan chain ordering.
- P.Gupta, J. Abraham and R.A. Parekhji, ``Improving Path Delay Coverage in Embedded Cores - Methodology and Experiments'', Texas Instruments Symposium on Test, 2001.
- P. Gupta, A. B. Kahng and S. Mantik, ``Routing-Aware Scan Chain Ordering'',
Proc. Asia and South Pacific Design Automation Conf., Jan.
2003, pp. 857-862.
- P. Gupta, A. B. Kahng and S. Mantik, ``A Proposal for Routing-Based Timing-Driven Scan Chain Ordering'',
Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 339-343.
- P. Gupta, A.B. Kahng, I.I. Mandoiu, and P. Sharma,
``Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault
Coverage'', Proc. IEEE/ACM Intl. Conference on Computer-Aided
Design, November 2003, pp. 754-759.
- P. Gupta, A.B. Kahng and S. Mantik, ``Routing Driven Scan Chain Ordering'', ACM Transactions of Design Automation of Electronic Systems.
- P. Gupta, A.B. Kahng, I.L. Mandoiu and P. Sharma, ``Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage'', IEEE Transactions on CAD.
Power Estimation and Reduction
I have worked on quantifying the error in dynamic power estimation in
CMOS circuits as done by conventional methods. Our experiments show
that incorrectly accounting for capacitive coupling can be a major
cause of discrepancy.
We have also proposed fast closed-form
expression based methods for power grid analysis and optimization
which can be used within a layout optimization flow. The proposed methods achieve almost perfect correlation with more involved numerical techniques and optimization achieves upto 30% reduction in power grid area.
Finally, we have investigated the use of small gate length biases to reduce leakage power and variability in a cell-based design context. This layout transparent technique can achieve upto 30% reduction in leakage and 40% reduction in variability at 130nm with potential improvements at 90nm and 65nm higher.
- P. Gupta and A. B. Kahng, ``Quantifying Error in Dynamic Power Estimation of CMOS Circuits'',
Proc. IEEE Intl. Symp. on Quality Electronic Design, March
2003, pp. 273-278.
- P. Gupta and A. B. Kahng, ``Efficient Design and Analysis of Robust Power Distribution Meshes'', Proc. Intl. Conf. on VLSI Design, Hyderabad, January 2006.
- P. Gupta, A.B. Kahng, P. Sharma and D. Sylvester, ``Selective Gate-Length Biasing for Cost-Effective R untime Leakage Reduction'', Proc. DAC, 2004.
- P. Gupta, A.B. Kahng and S. Shah, ``Standard Cell Library Optimization for Leakage Reduction'', Proc. IEEE/ACM DAC, 2006.
- P. Gupta, A.B. Kahng and S. Muddu, ``Quantifying Error in Dynamic Power Estimation of CMOS Circuits'', Journal of Analog Integrated Circuits and Signal Processing.
- P. Gupta, A.B. Kahng, P. Sharma and D. Sylvester, ``Gate-Length Biasing for Runtime Leakage Control'', IEEE Transactions on CAD .
- P. Gupta, A.B. Kahng and P. Sharma, ``A Practical Transistor-Level Threshold Voltage Assignment Methodology'', Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 261-265.
Systematic Variation Aware Design Methodologies
At IBM, we proposed a novel static timing methodology which correctly
takes into account effects of pattern dependent and focus dependent
variation. Isolated and dense lines print systematically
differently at best-focus condition and behave differently
through-focus. Though OPC and assist features try to correct for
these distortions, there is a large residual left resulting in as
much as 10% CD variation. We propose and implement a static timing
analysis flow and show up to 40% reduction in timing uncertainty
caused by CD variation. In a followup work, we use this nice property of focus-dependent CD variation to propose a novel design methodology of self-compensated design achieving 25% less area overhead compared to RDR approaches with same level of robustness.
In a separate work, we tried to quantify the impact of various layout design rules on actual manufacturability in terms of CD variation.
Conventional design automation models and algorithms
have been geared towards rectangular shaped wires and gates and hence
ill-equipped to handle the simulated wafer shapes for purposes of
We have proposed a full-chip timing and power analysis methodology including
both wires and gates to analyze such litho-simulated contours. It is
interesting to see that at 100nm lithographic defocus, leakage increases by up
to 68\%, cycle time improves by up to 14%, and dynamic power reduces by up to
2%. We have also proposed the first model for non-rectangular channels
which accounts for narrow width effects which has significantly less error that
the previous simplified models. We have also proposed simplified prediction models for lithographic error from drawn layout.
- F.-L. Heng, P. Gupta, R.L. Gordon, K. Lai and J.
Lee, `` Taming pattern and focus variation in VLSI design'', Proc. SPIE
Conf. on Design and Process Integration for Microelectronic
Manufacturing, Feb 2004.
- P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, ``Toward a Methodology for
Manufacturability Driven Design Rule Exploration'', Proc. DAC, 2004.
- P. Gupta and F.-L. Heng, ``Toward a Systematic-Variation Aware Timing Methodology'', Proc. DAC, 2004.
- P. Gupta, A.B. Kahng, S.V. Muddu, and S. Nakagawa ``Modeling edge placement error distribution in standard cell library'', Proc. SPIE Microlithography, 2006.
- P. Gupta, A.B. Kahng, Y. Kim, S. Shah, and D. Sylvester ``Modeling of non-uniform device geometries for post-lithography circuit analysis'', Proc. SPIE Microlithography, 2006.
- P. Gupta, A.B. Kahng, S. Nakagawa, S. Shah, and P. Sharma ``Lithography simulation-based full-chip design analyses'', Proc. SPIE Microlithography, 2006.
- P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester, ``Self-Compensating Design for Focus Variation'', Proc. Design Automation Conference, June 2005.
- F.-L. Heng, P. Gupta and J.-F. Lee, ``Through Process Layout Quality Metrics'', Proc. SPIE DPI, 2005.
- P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester ``Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation'', Proc. SPIE Microlithography, 2006.
- P. Gupta, A. B. Kahng, Y. Kim and D. Sylvester, ``Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation'', to appear in IEEE Transactions on CAD.
Placement for Improved Process Window
We have proposed perturbation of detailed placement of standard cells to
redistribute whitespace in order to remove the so-called ``forbidden pitches''
in the layout and make the layout more amenable to SRAF and etch dummy
insertion downstream. The proposed dynamic programming based algorithm used for
this purpose reduces lithographic edge placement errors in resist CD by
90%-100% and 70%-100% in etch CD.
Topography Aware OPC
We propose a novel method to drive OPC with a topography map of
the layout that is generated by CMP simulation. The wafer topography variations
result in local defocus, which we explicitly model in our OPC insertion and
verification flows by algorithmically partitioning the layout into multiple
defocus marking layers. The proposed topography-aware OPC yields 67%-80%
reduction in worst-case edge placement errors compared to conventional OPC.
- P. Gupta, A.B. Kahng and C.-H. Park, ``Manufacturing-aware design methodology for assist feature correctness'', Proc. SPIE DPI, 2005.
- P. Gupta, A. B. Kahng and C.-H. Park, ``Detailed Placement for Improved Depth of Focus and CD Control'', Proc. Asia and South Pacific Design Automation Conf., Jan. 2005, pp. 343-348.
- P. Gupta, A. B. Kahng and C.-H. Park,``Enhanced resist and etch CD control by design perturbation'', Proc. 25th BACUS Symposium on Photomask Technology and Management, October 2005.
- P. Gupta, A. B. Kahng and C.-H. Park, ``Detailed Placement for Enhanced Control of Resist and Etch CDs'', to appear in IEEE Transactions on CAD.
- P. Gupta, A.B. Kahng, C.-H. Park, K. Samadi and X. Xu, ``Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control'', Proc. SPIE PMJ, 2005.
- P. Gupta, A.B. Kahng, C.-H. Park, K. Samadi and X. Xu,
``Wafer Topography-Aware Optical Proximity Correction'', IEEE Transactions on Computer-Aided Design.
We proposed a wire-swizzling technique to reduce timing uncertainty
caused by capacitive coupling in long parallel buses. We show up to
31% reduction in worst-case delay.
- P. Gupta and A.B. Kahng,
``Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive
Coupling'', Proc. IEEE Intl. Conf. on VLSI Design, Jan 2004, to
Evaluating Interconnect Architectures
We propose a bandwidth-based metric to evaluate multi-layer interconnect stack architectures including via blockage estimates. We evaluate few publicly available 130nm and 90nm interconnect stacks.
- P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester, ``Investigation of Performance Metrics for Interconnect Stack Architectures'', Proc. ACM International Workshop on System-Level Interconnect Prediction, Feb. 2004, pp. 23-29.
We proposed heuristics for scheduling operations of a program on a
hypothetical completely reconfigurable processor. We extended this
work to a codesign setup wherein a general purpose microprocessor
communicates with FPGA based reconfigurable hardware. We proposed
simulated annealing and genetic algorithm based hardware-software
partitioning algorithms. The testbed was a modified MIPS simulator
running ADPCM code.
Signature Detection Using Adaptive Fuzzy Networks
- P. Gupta, N. Mangal, C.P. Ravikumar,
``Task Partitioning Between a General Purpose Microprocessor and
Reconfigurable Hardware'', 9th ACM/SIGDA International
Symposium on FPGAs, 2001.(Poster Paper)
- P. Gupta, N. Mangal, ``Operation Scheduling in a Reconfigurable Computing Environment'',
IEEE VLSI Design and Test Workshop, 1999, New Delhi.
We looked upon the problem of
online signature (cursive English alphabet) recognition.
Implementation was done in C. We used angle frequency histograms for
signature characterization. For recognition we used an adaptive
neuro-fuzzy inference system (ANFIS) with a hybrid learning rule.
Secure Digital Music
As a hobby project, we modified open-source mp3 players to support
a digitally encrypted and watermarked format which permits use-based
and time-based restricting of the song play.
As another hobby project, we developed a phonetic search engine for Indian languages based on a modified
Soundex algorithm and a database backend.