Puneet Gupta 
Publications 
Conference Papers

Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "Design
Sensitivities to Variability: Extrapolation and Assessments in Nanometer
VLSI",
(.ps),
(.pdf),
IEEE ASIC/SoC Conference, September 2002, pp. 411415.

P. Gupta, A. B. Kahng and S. Mantik, "RoutingAware Scan Chain Ordering",
(.ps),
(.pdf),(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2003, pp. 857862.

Y. Chen, P. Gupta, and A. B. Kahng, "PerformanceImpact Limited Dummy Fill
Insertion", (.ps),
(.pdf),
(.ppt),(.ppt),
Proc. SPIE Conf. on Design and Process Integration for
Microelectronic Manufacturing,
Feb. 2003.

P. Gupta and A. B. Kahng,"Quantifying Error in Dynamic Power Estimation of
CMOS
Circuits",
(.ps),
(.pdf),(slides),
Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003,
pp.
273278.

P. Gupta, A. B. Kahng and S. Mantik,"A Proposal for RoutingBased
TimingDriven
Scan Chain Ordering",
(.ps),
(.pdf),(.ppt),
Proc. IEEE Intl. Symp. on Quality Electronic Design,
March 2003, pp. 339343.
 Y. Chen, P. Gupta and A.B. Kahng,"PerformanceImpact Limited Area
Fill Synthesis", (.ps),
(.pdf),
Proc. IEEE/ACM Design Automation Conference June 2003
.
 P. Gupta, A.B. Kahng, D. Sylvester and J. Yang "A CostDriven
Lihographic Correction Methodology Based on OfftheShelf Sizing Tools",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Design Automation Conference June 2003.
 P. Gupta, A.B. Kahng, I.I. Mandoiu, and P. Sharma,
``LayoutAware Scan Chain Synthesis for Improved Path Delay Fault
Coverage'', Proc. IEEE/ACM Intl. Conference on ComputerAided
Design, November 2003, pp. 754759.
 P. Gupta and A.B. Kahng,
``ManufacturingAware Physical Design'', Proc. IEEE/ACM Intl.
Conference on ComputerAided Design, November 2003, (embedded
tutorial) pp. 681687.
 P. Gupta and A.B. Kahng,
``Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive
Coupling'', Proc. IEEE Intl. Conf. on VLSI Design, Jan 2004
.
 P. Gupta, F.L. Heng, M. Lavin, ``Merits of Cellwise
ModelBased OPC'', Proc. SPIE Conf. on Design and Process
gntegration for Microelectronic Manufacturing, Feb 2004.
 F.L. Heng, P. Gupta, R.L. Gordon, K. Lai and J.
Lee, `` Taming Focus Variation in VLSI Design'', Proc. SPIE
Conf. on Design and Process Integration for Microelectronic
ganufacturing, Feb 2004.
 P. Gupta, A.B. Kahng, Y. Kim and D. Sylvester, ``Investigation of
Performance Metrics for Interconnect Stack Architectures'', Proc.
g SLIP, 2004.
 P. Gupta and F.L. Heng, ``Toward a SystematicVariation Aware Timing Methodology'', Proc. DAC
 P. Gupta, A.B. Kahng, P. Sharma and D. Sylvester, ``Selective GateLength Biasing for CostEffective R
gntime Leakage Reduction'', Proc. DAC, 2004.
 P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, ``Toward a Methodology for Manufacturability Driven Design Rule Exploration'', Proc. DAC, 2004.

P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, ``PerformanceDriven OPC for Mask Cost Reduction'', Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 270275.

P. Gupta, A. B. Kahng and P. Sharma, ``A Practical TransistorLevel Threshold Voltage Assignment Methodology'', Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 261265.

P. Gupta, A. B. Kahng and C.H. Park, ``Detailed Placement for Improved Depth of Focus and CD Control'', Proc. Asia and South Pacific Design Automation Conf., Jan. 2005, pp. 343348.
 P. Gupta, A.B. Kahng and C.H. Park,
``Manufacturingaware design methodology for assist feature correctness'',
gem> Proc. SPIE DPI , 2005.
 F.L. Heng, P. Gupta and J.F. Lee,
``Through Process Layout Quality Metrics'',
gem> Proc. SPIE DPI , 2005.
 P. Gupta, A.B. Kahng, C.H. Park, K. Samadi and X. Xu,
``TopographyAware Optical Proximity Correction for Better DOF margin and CD Control'', Proc. SPIE PMJ, 2005.

P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, ``SelfCompensating Design for Focus Variation'', Proc. Design Automation Conference, June 2005.

P. Gupta, A. B. Kahng and C.H. Park,``Enhanced resist and etch CD control by design perturbation'', Proc. 25th BACUS Symposium on Photomask Technology and Management, October 2005.

P. Gupta, A.B. Kahng, S. Muddu, O.S. Nakagawa, C.H. Park,
``Modeling OPC Complexity for Design for Manufacturability'',
gem> Proc. 25th BACUS Symposium on Photomask Technology and Management, October 2005.

Y. Zhang, R. Gray, O.S. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler
``Interaction and balance of mask write time and design RET strategies''
Proc. SPIE Photomask Japan, 2005.

P. Gupta and A. B. Kahng,
``Efficient Design and Analysis of Robust Power Distribution Meshes'',
Proc. Intl. Conf. on VLSI Design, Hyderabad, January 2006.

P. Gupta, A.B. Kahng, S. Nakagawa, S. Shah, and P. Sharma
``Lithography simulationbased fullchip design analyses'',
Proc. SPIE Microlithography, 2006

P. Gupta, A.B. Kahng, Y. Kim, S. Shah, and D. Sylvester
``Modeling of nonuniform device geometries for postlithography circuit analysis'',
Proc. SPIE Microlithography, 2006.

P. Gupta, A.B. Kahng, S.V. Muddu, and S. Nakagawa
``Modeling edge placement error distribution in standard cell library'',
Proc. SPIE Microlithography, 2006.

P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester
``Selfcompensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation'',
Proc. SPIE Microlithography, 2006.

P. Gupta, A.B. Kahng and S. Shah,
``Standard Cell Library Optimization for Leakage Reduction'',
Proc. IEEE/ACM DAC, 2006.
 P. Gupta, A.B. Kahng, Y. Kim and S. Shah,
``Line End Shortening is not Always a Failure'', Proc. IEEE/ACM DAC (WACI Session), 2007.
 P. Gupta, A.B. Kahng, Y. Kim, S. Shah and D. Sylvester,
``Investigation of Diffusion Rounding for PostLithography Analysis'', Proc. IEEE/ACM ASPDAC , 2008.
 P. Gupta, A.B. Kahng, S. Shah, D. Sylvester, ``Shaping gate channels for improved devices'', Proc. SPIE Advanced Lithography , 2008.
 P. Gupta, K. Jeong, A.B. Kahng and C.H Park, ``Electrical Metrics for Lithographic LineEnd Tapering'', Proc. SPIE Photomask, Japan, 2008.
 P. Gupta and A.B. Kahng, ``Bounded Lifetime Integrated Circuits'', Proc. IEEE/ACM Design Automation Conference (WACI Session) , 2008.

J. Cong, P. Gupta and J. Lee, ``On the Futlity of Statistical Power Optimization'', to appear in Proc. IEEE/ACM ASPDAC , 2009.

L. Cheng, P. Gupta and L. He, ``Accounting for Nonlinear Dependence Using Function Driven Component Analysis'', to appear in Proc. IEEE/ACM ASPDAC, 2009.
 R.S. Ghaida and P. Gupta, ``DesignOverlay Interactions in Metal Double Patterning'', to appear in SPIE Advanced Lithography, 2009.
Invited Papers

D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang, "Toward
performancedriven red
uction of the cost of RETbased
lithography control"(Invited Paper), (.ps),
(.pdf),(.ppt),
Proc. SPIE Conf. on Design and Process Integration for
Microelectronic Manufacturing,
geb. 2003.
 P. Gupta, A.B. Kahng, C.H. Park,
P. Sharma, D. Sylvester and J. Yang,
g`Joining the Design and Mask Flows for Better and Cheaper Masks'', Proc. SPIE BACUS , 2004.
 P. Gupta, A.B. Kahng and C.H. Park,
``Improving OPC Quality Via Interactions Within the DesigntoManufacturing
gFlow'', Proc. SPIE PhotoMask Japan , 2005.

P. Gupta, A. B. Kahng, O.S. Nakagawa and K. Samadi, ``Closing the Loop in interconnect Analyses and Optimization: CMP Fill, Lithography and Timing'', Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., Octobor 2005.
Invited Talks and Tutorials
 P. Gupta and A.B. Kahng,
``ManufacturingAware Physical Design'', IEEE/ACM Intl.
Conference on ComputerAided Design, November 2003, (embedded
tutorial)
 P. Gupta and A.B. Kahng,
``CMP and DFM'', CMPMIC, 2005 (short tutorial)

P. Gupta,
``DFM Fundamentals'', WesCon , 2005 (short tutorial)
 R. Puri and P. Gupta, ``Impact Of Variability On VLSI Circuits'', short course, SPIE Advanced Lithography , 2007.
 P. Gupta, ``The Electrical Design Manufacturing Interface'', Electronic Design Processes Workshop, 2008.
 P. Gupta and C. Wu, ``Lithography and Memories: From Shapes to Electrical'', IEEE VLSI Test Symposium , 2008.
 D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu and N. Tamarapalli, ``DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction'', fullday tutorial, IEEE/ACM Design Automation Conference, 2008.
 P. Gupta, ``Challenges at 45nm and Beyond'', Panel Discussion, IEEE/ACM ICCAD, 2008.
Journal Papers
 P. Gupta, A.B. Kahng and S. Mantik, ``Routing Driven Scan Chain
Ordering'', ACM Transactions of Design Automation of Electronic
Systems, 2005
 P. Gupta, A.B. Kahng, I.I. Mandoiu and P. Sharma, ``LayoutAware
Scan Chain Synthesis for Improved Path Delay Fault Coverage'', IEEE
Transactions on CAD, 2005.
 P. Gupta, A.B. Kahng and S. Muddu, ``Quantifying Error in Dynamic Power Estimation of CMOS Circuits'',
Journal of Analog Integrated Circuits and Signal Processing, 2005.

P. Gupta, A.B. Kahng, P. Sharma and D. Sylvester,
``GateLength Biasing for Runtime Leakage Control'',
IEEE Transactions on CAD , 2006.
 P. Gupta, A.B. Kahng, C.H. Park, K. Samadi and X. Xu,
``Wafer TopographyAware Optical Proximity Correction'',
IEEE Transactions on ComputerAided Design, 2006.
 P. Gupta, A. B. Kahng, Y. Kim and D. Sylvester,
``SelfCompensating Design for Reduction of Timing and Leakage Sensitivity to
Systematic Pattern Dependent Variation'', IEEE Transactions
on CAD , 2007.
 P. Gupta, A. B. Kahng and C.H. Park, ``Detailed Placement for Enhanced Control of Resist and Etch CDs'', IEEE Transactions on CAD, 2007.
 P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, ``PerformanceDriven Optical Proximity Correction for Mask Cost Reduction'', SPIE Journal of Microlithography, Microfabrication and Microsystems, 2007.
Undergraduate Work
 P. Gupta, N. Mangal and C.P. Ravikumar,
"Task Partitioning Between a General Purpose Microprocessor and
Reconfigurable Hardware", ACM/SIGDA International Symposium on
FPGAs",
2001 (Poster paper).
 P. Gupta and N. Mangal,
"Operation Scheduling in Reconfigurable Computing Environment",
IEEE VLSI Design and Test Workshop, 1999.
.ps
 P.Gupta, J. Abraham and R.A. Parekhji,
"Improving Path Delay Coverage in Embedded Cores  Methodology and
Experiments", Texas Instruments Symposium on Test, 2001.
.ps
 Undergraduate Thesis. "Task Partitioning Between a General Purpose
Microprocessor and Reconfigurable Hardware"
.ps
 Winter Project "Rule Based Signature Detection and Verification"
!!!WARNING!!! MSWord
Patents
9 pending patents. 4 patent granted.
 ``Method for Correcting a Mask Layout'', US Patent No. 7,149,999
 ``Integrated circuit logic with self compensating block delays'', US Patent No. 7,084,476
 ``Method of IC fabrication, IC mask fabrication and program product'' (US Patent No. 7,353,492)
 ``Gatelength biasing for digital circuit optimization'', (US Patent No. 7,441,211)