Puneet Gupta Publications
Conference Papers
  1. Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI", (.ps), (.pdf), IEEE ASIC/SoC Conference, September 2002, pp. 411-415.
  2. P. Gupta, A. B. Kahng and S. Mantik, "Routing-Aware Scan Chain Ordering", (.ps), (.pdf),(.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2003, pp. 857-862.
  3. Y. Chen, P. Gupta, and A. B. Kahng, "Performance-Impact Limited Dummy Fill Insertion", (.ps), (.pdf), (.ppt),(.ppt), Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb. 2003.
  4. P. Gupta and A. B. Kahng,"Quantifying Error in Dynamic Power Estimation of CMOS Circuits", (.ps), (.pdf),(slides), Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 273-278.
  5. P. Gupta, A. B. Kahng and S. Mantik,"A Proposal for Routing-Based Timing-Driven Scan Chain Ordering", (.ps), (.pdf),(.ppt), Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 339-343.
  6. Y. Chen, P. Gupta and A.B. Kahng,"Performance-Impact Limited Area Fill Synthesis", (.ps), (.pdf), Proc. IEEE/ACM Design Automation Conference June 2003 .
  7. P. Gupta, A.B. Kahng, D. Sylvester and J. Yang "A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Design Automation Conference June 2003.
  8. P. Gupta, A.B. Kahng, I.I. Mandoiu, and P. Sharma, ``Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage'', Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2003, pp. 754-759.
  9. P. Gupta and A.B. Kahng, ``Manufacturing-Aware Physical Design'', Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2003, (embedded tutorial) pp. 681-687.
  10. P. Gupta and A.B. Kahng, ``Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling'', Proc. IEEE Intl. Conf. on VLSI Design, Jan 2004 .
  11. P. Gupta, F.-L. Heng, M. Lavin, ``Merits of Cellwise Model-Based OPC'', Proc. SPIE Conf. on Design and Process gntegration for Microelectronic Manufacturing, Feb 2004.
  12. F.-L. Heng, P. Gupta, R.L. Gordon, K. Lai and J. Lee, `` Taming Focus Variation in VLSI Design'', Proc. SPIE Conf. on Design and Process Integration for Microelectronic ganufacturing, Feb 2004.
  13. P. Gupta, A.B. Kahng, Y. Kim and D. Sylvester, ``Investigation of Performance Metrics for Interconnect Stack Architectures'', Proc. g SLIP, 2004.
  14. P. Gupta and F.-L. Heng, ``Toward a Systematic-Variation Aware Timing Methodology'', Proc. DAC
  15. P. Gupta, A.B. Kahng, P. Sharma and D. Sylvester, ``Selective Gate-Length Biasing for Cost-Effective R gntime Leakage Reduction'', Proc. DAC, 2004.
  16. P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, ``Toward a Methodology for Manufacturability Driven Design Rule Exploration'', Proc. DAC, 2004.
  17. P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, ``Performance-Driven OPC for Mask Cost Reduction'', Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 270-275.
  18. P. Gupta, A. B. Kahng and P. Sharma, ``A Practical Transistor-Level Threshold Voltage Assignment Methodology'', Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 261-265.
  19. P. Gupta, A. B. Kahng and C.-H. Park, ``Detailed Placement for Improved Depth of Focus and CD Control'', Proc. Asia and South Pacific Design Automation Conf., Jan. 2005, pp. 343-348.
  20. P. Gupta, A.B. Kahng and C.-H. Park, ``Manufacturing-aware design methodology for assist feature correctness'', gem> Proc. SPIE DPI , 2005.
  21. F.-L. Heng, P. Gupta and J.-F. Lee, ``Through Process Layout Quality Metrics'', gem> Proc. SPIE DPI , 2005.
  22. P. Gupta, A.B. Kahng, C.-H. Park, K. Samadi and X. Xu, ``Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control'', Proc. SPIE PMJ, 2005.
  23. P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, ``Self-Compensating Design for Focus Variation'', Proc. Design Automation Conference, June 2005.
  24. P. Gupta, A. B. Kahng and C.-H. Park,``Enhanced resist and etch CD control by design perturbation'', Proc. 25th BACUS Symposium on Photomask Technology and Management, October 2005.
  25. P. Gupta, A.B. Kahng, S. Muddu, O.S. Nakagawa, C.-H. Park, ``Modeling OPC Complexity for Design for Manufacturability'', gem> Proc. 25th BACUS Symposium on Photomask Technology and Management, October 2005.
  26. Y. Zhang, R. Gray, O.S. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler ``Interaction and balance of mask write time and design RET strategies'' Proc. SPIE Photomask Japan, 2005.
  27. P. Gupta and A. B. Kahng, ``Efficient Design and Analysis of Robust Power Distribution Meshes'', Proc. Intl. Conf. on VLSI Design, Hyderabad, January 2006.
  28. P. Gupta, A.B. Kahng, S. Nakagawa, S. Shah, and P. Sharma ``Lithography simulation-based full-chip design analyses'', Proc. SPIE Microlithography, 2006
  29. P. Gupta, A.B. Kahng, Y. Kim, S. Shah, and D. Sylvester ``Modeling of non-uniform device geometries for post-lithography circuit analysis'', Proc. SPIE Microlithography, 2006.
  30. P. Gupta, A.B. Kahng, S.V. Muddu, and S. Nakagawa ``Modeling edge placement error distribution in standard cell library'', Proc. SPIE Microlithography, 2006.
  31. P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester ``Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation'', Proc. SPIE Microlithography, 2006.
  32. P. Gupta, A.B. Kahng and S. Shah, ``Standard Cell Library Optimization for Leakage Reduction'', Proc. IEEE/ACM DAC, 2006.
  33. P. Gupta, A.B. Kahng, Y. Kim and S. Shah, ``Line End Shortening is not Always a Failure'', Proc. IEEE/ACM DAC (WACI Session), 2007.
  34. P. Gupta, A.B. Kahng, Y. Kim, S. Shah and D. Sylvester, ``Investigation of Diffusion Rounding for Post-Lithography Analysis'', Proc. IEEE/ACM ASPDAC , 2008.
  35. P. Gupta, A.B. Kahng, S. Shah, D. Sylvester, ``Shaping gate channels for improved devices'', Proc. SPIE Advanced Lithography , 2008.
  36. P. Gupta, K. Jeong, A.B. Kahng and C.-H Park, ``Electrical Metrics for Lithographic Line-End Tapering'', Proc. SPIE Photomask, Japan, 2008.
  37. P. Gupta and A.B. Kahng, ``Bounded Lifetime Integrated Circuits'', Proc. IEEE/ACM Design Automation Conference (WACI Session) , 2008.
  38. J. Cong, P. Gupta and J. Lee, ``On the Futlity of Statistical Power Optimization'', to appear in Proc. IEEE/ACM ASPDAC , 2009.
  39. L. Cheng, P. Gupta and L. He, ``Accounting for Non-linear Dependence Using Function Driven Component Analysis'', to appear in Proc. IEEE/ACM ASPDAC, 2009.
  40. R.S. Ghaida and P. Gupta, ``Design-Overlay Interactions in Metal Double Patterning'', to appear in SPIE Advanced Lithography, 2009.

Invited Papers

  1. D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang, "Toward performance-driven red uction of the cost of RET-based lithography control"(Invited Paper), (.ps), (.pdf),(.ppt), Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, geb. 2003.
  2. P. Gupta, A.B. Kahng, C.-H. Park, P. Sharma, D. Sylvester and J. Yang, g`Joining the Design and Mask Flows for Better and Cheaper Masks'', Proc. SPIE BACUS , 2004.
  3. P. Gupta, A.B. Kahng and C.-H. Park, ``Improving OPC Quality Via Interactions Within the Design-to-Manufacturing gFlow'', Proc. SPIE Photo-Mask Japan , 2005.
  4. P. Gupta, A. B. Kahng, O.S. Nakagawa and K. Samadi, ``Closing the Loop in interconnect Analyses and Optimization: CMP Fill, Lithography and Timing'', Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., Octobor 2005.

Invited Talks and Tutorials

  1. P. Gupta and A.B. Kahng, ``Manufacturing-Aware Physical Design'', IEEE/ACM Intl. Conference on Computer-Aided Design, November 2003, (embedded tutorial)
  2. P. Gupta and A.B. Kahng, ``CMP and DFM'', CMP-MIC, 2005 (short tutorial)
  3. P. Gupta, ``DFM Fundamentals'', WesCon , 2005 (short tutorial)
  4. R. Puri and P. Gupta, ``Impact Of Variability On VLSI Circuits'', short course, SPIE Advanced Lithography , 2007.
  5. P. Gupta, ``The Electrical Design Manufacturing Interface'', Electronic Design Processes Workshop, 2008.
  6. P. Gupta and C. Wu, ``Lithography and Memories: From Shapes to Electrical'', IEEE VLSI Test Symposium , 2008.
  7. D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu and N. Tamarapalli, ``DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction'', full-day tutorial, IEEE/ACM Design Automation Conference, 2008.
  8. P. Gupta, ``Challenges at 45nm and Beyond'', Panel Discussion, IEEE/ACM ICCAD, 2008.

Journal Papers

  1. P. Gupta, A.B. Kahng and S. Mantik, ``Routing Driven Scan Chain Ordering'', ACM Transactions of Design Automation of Electronic Systems, 2005
  2. P. Gupta, A.B. Kahng, I.I. Mandoiu and P. Sharma, ``Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage'', IEEE Transactions on CAD, 2005.
  3. P. Gupta, A.B. Kahng and S. Muddu, ``Quantifying Error in Dynamic Power Estimation of CMOS Circuits'', Journal of Analog Integrated Circuits and Signal Processing, 2005.
  4. P. Gupta, A.B. Kahng, P. Sharma and D. Sylvester, ``Gate-Length Biasing for Runtime Leakage Control'', IEEE Transactions on CAD , 2006.
  5. P. Gupta, A.B. Kahng, C.-H. Park, K. Samadi and X. Xu, ``Wafer Topography-Aware Optical Proximity Correction'', IEEE Transactions on Computer-Aided Design, 2006.
  6. P. Gupta, A. B. Kahng, Y. Kim and D. Sylvester, ``Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation'', IEEE Transactions on CAD , 2007.
  7. P. Gupta, A. B. Kahng and C.-H. Park, ``Detailed Placement for Enhanced Control of Resist and Etch CDs'', IEEE Transactions on CAD, 2007.
  8. P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, ``Performance-Driven Optical Proximity Correction for Mask Cost Reduction'', SPIE Journal of Microlithography, Microfabrication and Microsystems, 2007.

Undergraduate Work

  1. P. Gupta, N. Mangal and C.P. Ravikumar, "Task Partitioning Between a General Purpose Microprocessor and Reconfigurable Hardware", ACM/SIGDA International Symposium on FPGAs", 2001 (Poster paper).
  2. P. Gupta and N. Mangal, "Operation Scheduling in Reconfigurable Computing Environment", IEEE VLSI Design and Test Workshop, 1999. .ps
  3. P.Gupta, J. Abraham and R.A. Parekhji, "Improving Path Delay Coverage in Embedded Cores - Methodology and Experiments", Texas Instruments Symposium on Test, 2001. .ps
  4. Undergraduate Thesis. "Task Partitioning Between a General Purpose Microprocessor and Reconfigurable Hardware" .ps
  5. Winter Project "Rule Based Signature Detection and Verification" !!!WARNING!!! MS-Word
Patents
9 pending patents. 4 patent granted.
  1. ``Method for Correcting a Mask Layout'', US Patent No. 7,149,999
  2. ``Integrated circuit logic with self compensating block delays'', US Patent No. 7,084,476
  3. ``Method of IC fabrication, IC mask fabrication and program product'' (US Patent No. 7,353,492)
  4. ``Gate-length biasing for digital circuit optimization'', (US Patent No. 7,441,211)
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