UCLA CMOS Lab - Publications

Conference Papers

2011

Y. Wang, B.-C. Huang, M. Zhang, C. Miao, Y.-H. Xie and J.C.S. Woo, "High performance graphene FETs with self-aligned buried gates fabricated on Scalable patterned Ni-Catalyzed Graphene," VLSI Symp. Tech, 2011

2010

A. Tura and J.C.S. Woo, "Characterization of Tunneling Resistance in Vertical Tunneling FETs," 2010 International Conference on Solid State Devices and Materials, pp. 3-9, Sep. 2010

Hsu-Yu Chang; Jason C. S. Woo, "Enhancement of Stress Memorization Technique (SMT) by High Thermal Annealing Temperature," 2010 International Conference on Solid State Devices and Materials, 22-24 Sep. 2010

2009

Venkatagirish, N.; Tura, A.; Jhaveri, R.; Hsu-Yu Chang; Woo, J.;, "The Tunnel Source MOSFET: A Novel Asymmetric Device Solution for Ultra-low Power Applications," 2009 IEEE International Conference on IC Design and Technology, May 2009, pp. 155-159

Venkatagirish N., Ahmet Tura, Ritesh Jhaveri, Hsu-Yu Chang, Jason Woo, "The Tunnel Source n-MOSFET: A Novel Asymmetric Device for Low Power Applications," (Invited) 2009 International Conference on Solid State Devices and Materials, Sendai Japan, 2009, pp. 20-21

Jing Zhu, Jason C.S. Woo, "Graphene Channel Field-Effect Transistors with Schottky Tunneling Source and Drain," 2009 International Conference on Solid State Devices and Materials, Sendai Japan, 2009, pp. 1226-1227

Hsu-Yu Chang; Venkatagirish, N.; Tura, A.; Jhaveri, R.; Woo, J., "The SiGe heterojunction source PNPN n-MOSFET with SSOI for low power application," SOI Conference, 2009 IEEE International , pp.1-2, 5-8 Oct. 2009

2008

N. V. Girish, R. Jhaveri, Ahmet Tura, Jason C.S. Woo, "Novel Asymmetric MOSFET structures for Low Power Applications," 2008 IEEE Conference on Electron Devices and Solid-State Circuits, Hong Kong (2008)

Ritesh Jhaveri, N. V. Girish, Jason Woo, "Novel MOSFET Devices for RF Applications," Proceedings of the 9th International conference on solid state and integrated circuit technology, Shanghai (2008)

Gaurav Gupta, J. C. S. Woo, "Novel Asymmetric SiGe/Strained Silicon Heterojunction Channel MOSFET," International Conference on Solid State Devices and Materials, Tsukuba, Japan, Sept. 2008

2007

Jing Zhu, J. C.-S. Woo, "A Novel Graphene Channel Field Effect transistor with Schottky Tunneling Source and Drain," 37th European Solid-State Device Research Conference ,2007, Munich, Germany.

Jintae Kim; Jhaveri, R.; Woo, J.; Chih-Kong Ken Yang;, "Device-circuit co-optimization for mixed-mode circuit design via geometric programming," IEEE/ACM International Conference on Computer-Aided Design, 2007 (ICCAD 2007), Nov. 2007

Ritesh Jhaveri, Jason C. S. Woo, "Analog Performance of Asymmetric Schottky Tunneling Source nFET for RF and Mixed-Mode Applications," International Conference on Solid State Devices and Materials, Tsukuba, Japan, Sept. 2007.

2006

Ritesh Jhaveri, Y.-L. Chao, J. C.-S. Woo, "Novel MOSFET Devices for RF Circuits Applications," Proceedings of the 8th International conference on solid state and integrated circuit technology, Shanghai (2006)

Y.-L. Chao, J. C.-S. Woo, "Reduction of Parasitic Resistance of Self-Aligned Copper Germanide for Germanium p-MOSFETs," International Conference on Solid State Devices and Materials, Yokohoma, Japan, Sept. 2006.

Ritesh Jhaveri, J. C.-S. Woo, "Schottky Tunneling Source MOSFET Design for Mixed Mode Applications," 36th European Solid-State Device Research Conference ,2006, Montreux, Switzerland.

2005

Dimitropoulos, D.; Jhaveri, R.; Claps, R.; Raghunathan, V.; Woo, J.C.S.; Jalali, B., "Dimensional scaling of nonlinear optical absorption insilicon waveguides," Proceedings of the conference on Lasers and Electro-Optics, vol. 1, 366-368, 2005.

Jun Yuan, Jason C.S. Woo, "Realization of a metal split gate by gate full ni-silicidation process for MOSFET RF/Analog applications," SSDM, Japan, Sep. 2005.

Jun Yuan, N. V. Girish, R. Jhaveri, Tura A, Jason C.S. Woo, "Novel device structures for sub-25nm generation," 2005 IEEE Conference on Electron Devices and Solid-State Circuits. IEEE. 2005, pp. 5-7. Piscataway, NJ, USA.

Y.-L. Chao, R. Scholz, J. C.-S. Woo, "Gate Stack Integration of Germanium Oxynitride for Germanium MOSFETs," Sept. 05, International Conference on Solid State devices and Materials, Kobe, Japan, 2005.

Youngwoo Park and Jason C. S. Woo, "A Novel Simplified Process for Self Aligned Planar Wrapping Gate FET's with Directionally Crystallized Si Channel Processed via Sequential Lateral Solidification," International Conference on Solid State Devices and Materials, Kobe, Japan,pp.614-615, Sep. 2005.

2004

N. V. Girish, R. Jhaveri, J. C. S. Woo, "Tunnel Source MOSFET: A Novel High Performance Transistor," Proceedings of 2004 IEEE Si Nanoelectronics Workshop, 2004.

Kim, S.-D., Johnson, J.B., Yuan, J., Woo, J. C. S., "Optimization of Recessed and Elevated Silicide Source/Drain Contact Structure Using Physical COmpact Resistance Modeling and SImulation in Ultra-Thin Body SOI MOSFETs," International Conference on Simulation of Semiconductor Processes and Devices, Sept. 2-4, 2004.

Y.-L. Chao, R. Scholz, M. Reiche, U. Goesele, J. C.-S. Woo, "Fabrication and Characteristics of Germanium-on-Insulator," extended abstract of the 2004 International Conference on Solid State Devices and Materials, 2004, pp. 224.

M. Gupta, J. C.-S. Woo, "Effects of Gate Oxide Scaling and Gate Leakage Currents on sample and hold circuits," extended abstract of the 2004 International Conference on Solid State Devices and Materials, 2004, pp. 416.

Chih-kong ken yang, Mayank Garg, J. C.-S. Woo, "CMOS Scaling on I/ODesign," extended abstract of the 2004 International Conference on Solid State Devices and Materials, 2004, pp. 134.

Y.-L. Chao, S. Prussin, R. Scholz, J. C.-S. Woo, "Dopant Activation in Bulk Ge and Germanium-on-Insulator," 2004 MRS Winter Meeting.

Jun Yuan, Grant Pan, Yu-Lin Chao, Jason C.-S. Woo, "Nickel Silicide Workfunction Tuning Study in Metal-Gate CMOS Applications," 2004 MRS Winter Meeting.

Sushant S. Suryagandh, Mayank Garg, M. Gupta, Jason C. S. Woo, "Analog Performance of Scaled Bulk and SOI MOSFETs," (Invited), 7th International Conference on Solid State and Integrated Circuit Technology (ICSICT), October 2004.

Mayank Gupta, Jason Woo, "Device design for sub-90 nm MOSFETs for sample and hold circuits," proceedings of the 34th European solid state device research conference, 2004, pp. 377-380.

2003

S.S. Suryagandh, M. Garg, and J.C.S. Woo, "A detailed analysis of SOI MOSFETs for SOC design," Proceedings of the IEEE International SOI Conference, Sept. 29-Oct. 2, 2003, pp. 147-148.

Jun Yuan and Jason C. S. Woo, "Split Gate Engineering for RF/Analog Application In Sub 50 nm NMOSFET," International Conference on Solid State Devices and Materials, Tokyo, Japan, Sep. 2003. pp.436-437.

Jae-Kwan Park* and Jason C. S. Woo, "A New One-Transistor One-Bipolar (1T1B) Capacitor-Less DRAM Cell," Extended Abstracts of the 2003 international conference on Solid State Devices and Materials, Tokyo, 2003 pp.428-429.

2002

Gupta Mayank, Vidya V, Ramgopal Rao V, To KH, Woo JCS. "Optimization of sub 100 nm Gamma -gate Si-MOSFETs for RF applications," [Conference Paper] Proceedings of the Eleventh International Workshop on the Physics of Semiconductor Devices (SPIE Vol.4746). SPIE. Part vol.1, 2002, pp.652-6 vol.1. Washington, DC, USA.

Jun Yuan, Peter M. Zeitzoff, J.C.S. Woo "Source/Drain Parasitic Resistance Role and Electric Coupling Effect in sub 50nm MOSFET Design," Proceedings of the 32th European Solid-State Device Reseach Conference , 2002, Florence, Italy, p503-506

Neeraj K. Jha, V. Ramgopal, J.C.S Woo, "Optimization of SIngle Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability," Proceedings of the 32th European Solid-State Device Reseach Conference , 2002, Florence, Italy, p603-606

Seong-Dong Kim, Sungkwon Hong, Jae-Kwan Park, and Jason C. S. Woo, "Modeling and analysis of gate line edge roughness effect on CMOS scaling towards deep nanoscale gate length," Extended Abstracts of International Conference on Solid State Devices and Materials (SSDM2002), pp. 20-21, 2002 (Nagoya, Japan)

Seong-Dong Kim and Jason C. S. Woo, "Detailed Modeling of Source/Drain Parasitics and Their Impact on MOSFETs Scaling," International Workshop on Junction Technology (IWJT2002), pp. 1-2, December 2002 (Invited Paper, Tokyo, Japan)

2001

J. C.S. Woo "Device Challenges for Sub-150 nm CMOS," ULSI Process Integration II, p489-494, 2001

C.M.Park, S.D. Kim, Yun Wang, Somit Talwar , J. C.S. Woo "50nm SOI CMOS Transistors with Ultra Shallow Junction using Laser Annealing and Pre-Amorphization Implanation," 2001 Symposium on VLSI Technology Digest of Technical Papers, p.69 - p.70

Hemant V. Deshpande , B. Cheng, Jason C.S. Woo "Deep Sub-Micron CMOS device design for Low Power Analog Application," 2001 Symposium on VLSI Technology Digest of Technical Papers, p.87 - p.88

Hemant V. Deshpande ,Jason C.S. Woo "Novel Sub-25nm Devices," 2001 6th international conference on solid state and integrated circuit technology proceedings. P521-524

Jae-Kwan Park, Deshpande HV, Woo JCS. "Enhanced subthreshold leakage current due to impact ionization in deep sub-100nm N-channel double-gate MOSFETs," [Conference Paper] 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207). IEEE. 2001, pp.147-8. Piscataway, NJ, USA.

K.H. To and J.C.S Woo, "A T-gate MOSFET with Reduced Channel Length by Inverted Sidewalls for sub-100nm RF Application," Extended Abstracts of the 2001 international conference on Solid State Devices and Materials, p 152-153

Jae-Kwan Park, H.V. Deshpande, and J. C. S. Woo, "The Effect of Impact Ionization on the Subthreshold Leakage Current in N-Channel Double-Gate SOI Transistors," 31th European Solid-State Device Research Conference ,2001, Nuremberg, Germany.

2000

S. D. Kim, C.-M Park,and J.C.S. Woo, "Advanced Model and Analysis for Series Resistance in Sub-100nm CMOS Including Poly Depletion and Overlap Doping Gradient Effect," IEEE IEDM Technical Digest, pp. 54-55 , December 2000.

Seong-Dong Kim, Cheol-Min Park, Jason C.S. Woo " Modeling of the Series Resistance for Below 100nm MOSFET Regime," Extended Abstracts of the 2000 international conference on Solid State Devices and Materials, Sendai, 2000 pp.212-213

C.M.Park, K.Min, S.D. Kim, S.A. Prussin , M.K. Han, J. C.S. Woo, "Characteristics of Boron and Arsenic Ultra-Shallow Junction Using Laser Annealing with Pre- Amorphization Implantation," Extended Abstracts of the 2000 international conference on Solid State Devices and Materials, Sendai, 2000 pp.404-405

Hemant V. Deshpande , B. Cheng, Jason C.S. Woo "Improvement of Flicker Noise in Lateral Asymmetric Channel N-MOSFET for Sub-Micron Analog Application," Proceedings of the 30th European Solid-State Device Research Conference, Ireland, 2000 p.496-p.499

Hemant V. Deshpande , B. Cheng, Jason C.S. Woo "Sub-micron fully depleted lateral asymmetric channel SOI MOSFETs for analog and mixed mode applications," Proceedings IEEE International SOI Conference, 2000, p.54-p.55

1999

K.H. To , and J.C.S. Woo, "High PerformanceSub-0.1m m SOI Polysilicion Spacer Gate MOSFETs Using Large Angle Tilted Implant for Drain Engineering," IEEE International SOI Conference Proceedings , pp. 95-95, October 1999.

Y.-C. Tseng, W.M. Huang, C. Hwang, P. Welch, and J.C.S. Woo, "Temperature Dependence of AC Floating Body Effect in PD SOI nMOS,"IEEE International SOI Conference Proceedings , pp. 26-27, October 1999.

L.P. Ren, B. Cheng , and J.C.S. Woo, "Advanced Silicide for Sub-0.18mm CMOS on Ultra-thin (35mm) SOI," IEEE International SOI Conference Proceedings, pp. 88-89, October 1999.

K.H. To, and J.C.S. Woo, "60nm G -gate MOSFETs with Self-aligned Drain Extension Formed by Solid Phase Diffusion," Device Research Conference Digest, pp. 24-25, 1999.

B. Cheng, A. Inani, R. Rao, and J.C.S. Woo, "Channel Engineering for High Speed Sub-1.0V Power Supply Deep Sub-micron CMOS," Symposium on VLSI Technology, Digest of Technical Papers, pp. 69-70, June 1999.

Y.-C. Tseng, W.M. Huang, M. Mendicino, P. Welch, V. Ilderem, and J.C.S. Woo, "Minimizing Body Instability in Deep Sub-micron SOI MOSFETs for Sub-1 V RF Application," Symposium on VLSI Technology, Digest of Technical Papers, pp. 27-28, June 1999.

1998

A. Inani, V. Rao, B. Cheng, M. Cao, P. Voorde, W. Greene, and J.C.S. Woo, "Performance Considerations in Using High-k Dielectrics for Deep Sub-Micron MOSFETs," Extended Abstracts of the 1998 International Conference on Solid State Devices and Materials, pp. 94-95, September 1998.

Y.-C. Tseng, W.M. Huang, D. Diaz, and J.C.S. Woo, "Distortion Analysis of SOI MOSFETs for Analog Applications," Extended Abstracts of the 1998 International Conference on Solid State Devices and Materials , pp. 316-317, September 1998.

K.-H. To and J.C.S. Woo, "Sub-0.1um Sidewall Gate MOSFET with Large Angle Tilt Implanted Drain," 28th European Solid-State Device Research Conference pp. 160-163, September 1998.

B. Cheng, M. Cao, P. Voorde, W. Greene, H. Stork, Z. Yu, and J.C.S. Woo, "Design Considerations of High-k Dielectrics and Metal Gate Electrodes for Sub-0.1um MOSFETs," 28th European Solid-State Device Research Conference pp. 308-311, September 1998. B.

Cheng, V. Rao, B. Ikegami, and J.C.S. Woo, "Realization of 0.1um Asymmetric Channel MOSFETs with Excellent Short-Channel Performance and Reliability," 28th European Solid-State Device Research Conference pp. 520-523, September 1998.

Y.-C. Tseng, Huang, T.M.; Monk, T.; Diaz, T.; Ford, T.M.; Woo, J.C.S.; "Comprehensive study on AC characteristics in SOI MOSFETs for analog applications," Symposium on VLSI Technology, Digest of Technical Papers, pp. 112-113, June 1998.

L.P. Ren, P. Liu, G.Z. Pan, and J.C.S. Woo, "A Novel Low Temperature Self-Aligned Ti Silicide Technology for Sub-0.18um and Beyond CMOS Devices," Spring MRS Abstract, pp. 373-374, 1998.

1997

T.C. Hsiao, A. Wang, K. Saraswat, and J.C.S. Woo, "An Alternative Gate Electrode Material of Fully Depleted SOI CMOS for Low Power Applications," IEEE International SOI Conference Proceedings, pp. 20-21, October 1997.

Y.-C. Tseng, W.M. Huang, B. Ikegami, D. Diaz, J.M. Ford, and J.C.S. Woo, "Local floating Body Effect in Body-Grounded SOI nMOSFETs," IEEE International SOI Conference Proceedings, pp. 26-27, October 1997.

J. Seo, J.C.S. Woo, W. Maszara, and P. Vasudev, "The Early Breakdown Characteristics of Thin Gate Oxide on SOI Wafers," IEEE International SOI Conference Proceedings, pp. 52-53, October 1997.

Z. Li and J.C.S. Woo, "A General Physical Model for Short-Channel Double-Gate SOI MOSFETs," IEEE International SOI Conference Proceedings, pp. 86-87, October 1997.

T.C. Hsiao, P. Liu, W. Lynch, and J.C.S. Woo, "Source/Drain Engineering with Ge Large Angle Tilt Implantation and Pre-Amorphization to Improve Current Drive and Alleviate Floating Body Effects of Thin Film SOI MOSFETs," 27th European Solid-State Device Research Conference pages 516-519, September 1997.

Y.-C. Tseng, S.C. Chin, and J.C.S. Woo, "The Impact of SOI MOSFETs on Low Power Digital Circuits," International Symposium on Low Power Electronics and Design , pages 243-246, August 1997.

T.C. Hsiao, P. Liu, and J.C.S. Woo, "An Advanced Ge Pre-Amorphization Salicide Technology for Sub-Quarter Micrometer SOI CMOS Devices," Symposium on VLSI Technology, Digest of Technical Papers, pp. 95-96, June 1997.

Y.-C. Tseng, W.M. Huang, J. Babcock, J.M. Ford, and J.C.S. Woo, "Correlation Between Low-Frequency Noise Overshoot in SOI MOSFETs and Frequency Dependence of Floating Body Effect," Symposium on VLSI Technology, Digest of Technical Papers, pp. 99-100, June 1997.

1996

Z. Zhou, B. Pain, J.C.S. Woo, and E. Fossum, "A Digital CMOS Active Pixel Image Sensor for Multimedia Applications", Detectors, Focal Plae Arrays, and Applications, Proceedings of the SPIE: The International Society for Optical Engineering, Volume 2894, pp. 282-288, November 1996.

B. Cheng and J.C.S. Woo, "Inversion Hole Mobility in Fully Depleted SOI PMOS FET's: Measurement and Modeling," IEEE International SOI Conference Proceedings, pp. 64-65, October 1996.

Y.-C. Tseng, J. Collett, T.O. Vu, J. Cable, and J.C.S. Woo, "Analysis of Edge Effects in the Mesa Isolatted nMOS SOI," IEEE International SOI Conference Proceedings, pp. 90-91, Octobor 1996.

T.C. Hsiao, P. Liu, and J.C.S. Woo, "A Novel Salicide Technology for Thin Film SOI MOSFET's Using Ge Pre-Amorphization," IEEE International SOI Conference Proceedings, pp. 126-127, October 1996.

S.C. Chin, Y.-C. Tseng, and J.C.S. Woo, "Parasitic Bipolar Turn-On of PD-SOI MOSFETs in Dynamic Logic Circuits," IEEE International SOI Conference Proceedings, pp. 144-145, Octobor 1996.

C.Y. Hwang, J. Gillick ,C. Jenq, B. Hammond, and J.C.S. Woo, "Bias Dependent NMOS Hot-Carrier Reliability and Lifetime Over a Wide Temperature Range," Proceedings of the Second European Workshop on Low Temperature Electronics, pp. 25-28, June 1996.

B. Cheng and J.C.S. Woo, "Measurement and Modeling of the N-Channel and P-Channel MOSFET's Inversion Layer Mobility at Room and Low Temperature Operation," Proceedings of the Second European Workshop on Low Temperature Electronics, pp. 43-46, June 1996.

C.Y. Hwang, C. Jenq, B. Hammond, J. Gillick, and J.C.S. Woo, "Process Modification for Improved Low Temperature Performance," Proceedings of the Second European Workshop on Low Temperature Electronics, pages 193-198, June 1996.

J. Wang-Ratkovic, W. Huang, B. Hwang, M. Racanelli, J. Foerstner, and J.C.S. Woo, "Novel Device Lifetime Behavior and Hot-Carrier Degradation Mechanisms Under Vgs = Vth Stress for Thin-Film SOI nMOSFETs," IEEE IEDM Technical Digest, pp. , December 1995.

V.M. Chen and J.C.S. Woo, "A Low Thermal Budge, Fully Self-Aligned Lateral BJT on Thin Film SOI Substrate for Low Power BiCMOS Applications," VLSI Symposium on Technology, Digest of Technical Papers, pp. 133-134, June 1995.

1994

V.M. Chen and J.C.S. Woo, "A New Approach to Implement 0.1 um MOSFET on Thin-Film SOI Substrate with Self-Aligned Source-Body Contact," IEEE IEDM Technical Digest, pp. 657-660, December 1994.

J. Wang, B. Hwang, M. Racanelli, J. Foerstner, and J.C.S. Woo, "Hot-Carrier-Injection (HCI) Immunity Under High Drain Stress of Thin-Film SOI n-MOSFETs Fabricated on SIMOX and BESOI Substrates," IEEE International SOI Conference Proceedings, pp. 129-130, October 1994.

V.M. Chen and J.C.S. Woo, "A CMOS-Compatible, Low Power, Low Noise Gated BJT on TFSOI Substrate," VLSI Symposium on Technology, Digest of Technical Papers, pp. 35-36, June 1994.

I. Groves, G. Brown, G. Pollack, K. Green, L. Dawson, A. D'Souza, C. Lin, M. Song, C. Hwang, J.C.S. Woo, and K.MacWilliams, "One-Micrometer, Radiation-Hardened Complementary Metal Oxide Semiconductor for Cryogenic Analog Applications," Infrared Readout Electronics II, Proceedings of SPIE: The International Society for Optical Engineering, Volume 2226, pp. 72-84, April 1994.

1993

M. Song, K.P. MacWilliams, J. Scarpulla, D. Swanson, J.S. Cable, and J.C.S. Woo, "Cryogenic pMOS Hot Carrier Rebound and Degradation," IEEE IEDM Technical Digest, pp. 519-522, December 1993.

N. Kistler and J.C.S. Woo, "Symmetric CMOS in Fully Depleted Silicon-on-Insulator using p+-Polysilicon Si-Ge Gate Electrodes," IEEE IEDM Technical Digest , pp. 727-730, December 1993.

D. Nayak, J.C.S. Woo, J.S. Park, K.L. Wang, and K.P. MacWilliams, "Hole Confinement in Si/GeSi/Si Quantum Well on SIMOX," Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, September 1993.

D. Nayak, J.C.S. Woo, J.S. Park, K.L. Wang, and K.P. MacWilliams, "High-Mobility p-Channel MOSFET on Strained Si," Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, September 1993.

E. P. Ver Ploeg, C. Nguyen, S. Wong, J.D. Plummer, N. Kistler, and J.C.S. Woo, "First Direct Measurement for Parasitic Lateral Bipolar Transistors in Fully-Depleted SOI MOSFETs," Device Research Conference Proceedings , pp. IIA-5, 1993.

1992

D. Nayak, J.C.S. Woo, G. Yabiku, K.P. MacWilliams, J.S. Park, and K.L. Wang, "High Performance GeSi Quantum-Well PMOS on SIMOX," IEEE IEDM Technical Digest, pp. 777-780, December 1992.

M. Song, K.P. MacWilliams, J.S. Cable, and J.C.S. Woo, "Bias and Temperature Dependence of Hot Carrier Lifetime from 77K to 300K," IEEE IEDM Technical Digest, pp. 707-710, December 1992.

E. P. Ver Ploeg, T. Watanabe, N. Kistler, J.C.S. Woo, and J.D. Plummer, "Elimination of Bipolar-Induced Breakdown in Fully-Depleted SOI MOSFET's," IEEE IEDM Technical Digest , pp. 337-340, December 1992.

D. Nayak, J.C.S. Woo, J.S. Park, K.L. Wang, and K.P. MacWilliams, "High-Mobility p-Channel MOSFET on Strained Si," High-Mobility GeSi Quantum-Well PMOS on SIMOX," IEEE SOS/SOI Technical Conference, pp. 100-101, October 1992.

N. Kistler, E. Ver Ploeg, J.C.S. Woo, and J. Plummer, "Dependence of Fully Depleted SOI MOSFET Breakdown Voltage on Film Thickness and Channel Length," IEEE SOS/SOI Technical Conference, pp. 128-129, 1992.

1991

D. Nayak, K. Kamjoo, J.S. Park, J.C.S. Woo, and K.L. Wang, "Rapid Iso-Thermal Processing of Strained GeSi Layers," Spring MRS Abstract, pp. 151, 1991.

J. Cable, J. Liao, and J.C.S. Woo, "Improvements in Rapid Thermal Oxide/Reoxidized Nitrided Oxide (ONO) Films Using NF3," Spring MRS Abstract, pp. 162-163, 1991.

J.T. Hsu, J. Wang, J.C.S. Woo, and C.R. Viswanathan, "Flicker Noise in Thin Film Fully Depleted SOI MOSFET's," IEEE SOS/SOI Technical Conference , pp. 30-31, 1991.

J. Chang, D. Nayak, V.K. Raman, J.C.S. Woo, J. Park, K.L. Wang, and C.R. Viswanathan, "Low Frequency Noise in Quantum-Well Ge$_x$Si$_{1-x}$ pMOSFET's," 21th European Solid-State Device Research Conference, pp. 19-22, September 1991.

D. Nayak, J.C.S. Woo, J.S. Park, K.L. Wang, and K.P. MacWilliams, "Channel Mobility of GeSi Quantum-Well p-MOSFET's," Symposium on VLSI Technology, Digest of Technical Papers, pp. 107-108, June 1991.

1990

M. Song, J.S. Cable, K.P. MacWilliams, and J.C.S. Woo, "Dependence of LDD Device Optimization on Stressing Parameters at 77K," IEEE IEDM Techical Digest, pp. 223-226, December 1990.

J. Wang, N. Kistler, J. Woo, and C.R. Viswanathan, "Threshold Voltage Instability at Low Temperatures in Partially Depleted Thin Film SOI MOSFET's," IEEE SOS/SOI Technical Conference Proceedings, pp. 91-92, October 1990.

D. Nayak, J.C.S. Woo, J. Park, K.L. Wang, and K.P. MacWilliams, "Modulation-Doped p-Channel Ge{x}Si{1-x} MOSFET," Device Research Conference Proceedings, pages VIA-1, June 1990.

N. Kistler, J.C.S. Woo, and P.K. Vasudev, "Subthreshold Kink Effect in Fully Depleted SOI MOSFET's," Device Research Conference Proceedings, pp. IIB-6, June 1990.

D. Nayak, K. Kamjoo, J. Park, J.C.S. Woo, and K.L. Wang, "Rapid Thermal Oxidation of GeSi Strained Layers," Spring MRS Abstract, pp. 510, 1990. 1989:

N. Kistler, J.C.S. Woo, K. Terrill, and P.K. Vasudev, "Characterization of MOSFETs on Very Thin SOI at Temperatures from 77K to 350K," IEEE SOS/SOI Technical Conference Proceedings, pp. 56-57, 1989.

Journal Articles

2011

Bo-chao Huang, Ming Zhang, Yanjie Wang and Jason Woo, "Contact Resistance in Top-gated graphene Field-Effect Transistors," Applied Physics Letters, vol.99, 032107, July 2011.

Hsu-Yu Chang and Jason C. S. Woo, "The Improvement of Output Characteristics in Tensile Strained-Si-on-Insulator NMOSFET by Channel Band Gap Adjustment," IEEE Elec. Dev. Lett, vol.32, no.8, August 2011, pp.1032-1034.

Ahmet Tura, Zhenning Zhang, Peichi Liu, Ya-Hong Xie, and Jason C. S. Woo, "Vertical Silicon p-n-p-n Tunnel nMOSFET With MBE-Grown Tunneling Junction," IEEE Transactions on Electron Devices, vol. 58, no. 7, July 2011, pp. 1907-1913.

Jintae Kim, Ritesh Jhaveri, Jason Woo, C.-K. Ken Yang, "Circuit-Level Performance Evaluation of Schottky Tunneling Transistor in Mixed-Signal Applications," IEEE Transactions on Nanotechnology, vol. 10, no.2, March 2011, pp.291-299.

Jhaveri Ritesh, Nagavarapu Venkatagirish, Jason C. S. Woo, "Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor," IEEE Transactions on Electron Devices, vol.58, no.1, Jan. 2011, pp.80-86.

2010

Matthew Mecklenburg, Jason Woo, B.C. Regan, "Tree-level electron-photon interactions in graphene," Phys. Rev. B 81, 245401, 2010.

A. Tura and J.C.S. Woo, "Performance Comparison of Silicon Steep Subthreshold FETs," IEEE Transactions on Electron Devices, vol. 57, no. 6, June 2010, pp. 1362-1368.

Yanjie Wang; Congqin Miao; Bo-chao Huang; Jing Zhu; Wei Liu; Youngju Park; Ya-hong Xie; Woo, J.C.S.; , "Scalable Synthesis of Graphene on Patterned Ni and Transfer," Electron Devices, IEEE Transactions on , vol.57, no.12, pp.3472-3476, Dec. 2010

Zhu, J.; Jhaveri, R.; Woo, J. C. S.; , "The effect of traps on the performance of graphene field-effect transistors," Applied Physics Letters , vol.96, no.19, pp.193503-193503-3, May 2010

2009

Jhaveri, R.; Nagavarapu, V.; Woo, J.C.S.;, "Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications," IEEE Transactions on Electron Devices, vol.56, no.1, January 2009, pp.93-99.

Venkatagirish Nagavarapu; Ahmet Tura; Ritesh Jhaveri; Hsu-Yu Chang; J.C. Woo;, "Asymmetric Tunneling Devices for Low Power ULSI," ECS Trans., Vol.22, no.1, 2009, pp.273-279.

Jing Zhu; Wei Liu; Yanjie Wang; Bo-Chao Huang; Ya-Hong Xie; Jason Woo;, "Systhesis and Devices of Graphene," ECS Trans., Vol.25, no.7, 2009, pp.495-501.

2008

Nagavarapu, V.; Jhaveri, R.; Woo, J.C.S.;, "The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor," IEEE Transactions on Electron Devices, vol.55, no.4, April 2008, pp.1013-1019.

2007

Yu-lin Chao; Woo, J.C.S.;, "Source/Drain Engineering for Parasitic Resistance Reduction for Germanium p-MOSFETs," IEEE Transactions on Electron Devices, vol.54, no. 10, Oct. 2007, pp.2750-2755.

2006

Y. -L. Chao, Y. Xu, R. Scholz, and Jason C.S. Woo, "Characterization of Copper Germanide as Contact Metal for Advanced MOSFETs," IEEE Elec. Dev. Lett., Vol. 27, No. 7, p. 549, July 2006.

Yu-Lin Chao, Roland Scholz, Manfred Reiche, Ulrich Goesele, Jason C.S. Woo, "Characteristics of Germanium-on-Insulators Fabricated by Wafer Bonding and Hydrogen-Induced Layer Splitting," JJAP, vol. 45, no. 11, p. 8565, 2006.

2005

N. V. Girish, Ritesh Jhaveri, J. C. S. Woo, "Asymmetric Tunneling Source MOSFETS: A Novel Device Solution for sub-100nm CMOS Technology," International Journal of High Speed Electronics and Systems, Vol. XX, no. X, 1-8, (2005)

Seong-Dong Kim, Cheol-Min Park and Jason C.S. Woo. "Formation and control of box-shaped ultra-shallow junction using laser annealing and pre-amorphization implantation," Solid-State Electronics, vol.49, no.1, Jan. 2005, pp.131-135. Publisher: IEEE, USA.

Y.-L. Chao, Q.-Y. Tong, T.-H. Lee, M. Reiche, R. Scholz, J. C.-S. Woo, U. Goesele, "NH4OH Effects on Low Temperature Bonding Energy Enhancement," Electrochemical and Solid State Letters, Vol. 8, G74, March 2005.

Y.-L. Chao, S. Prussin, R. Scholz, J. C.-S. Woo, "Preamorphization Implantation-Assisted Boron Activation in bulk germanium and germanium-on-insulator," Applied Physics Letters, Vol. 87, 142102, Oct, 2005.

D. Dimitripoulos, R. Jhaveri, R. Claps, J. C. S. Woo and B. Jalali, "Carrier Lifetime in Silicon Raman Laser," Applied Physics Letters, vol 86, 071115 (February 2005)

Jun Yuan, Jason C. S. Woo, "Tunable work function in fully nickel silicided polysilicon gates for metal gate MOSFET applications," IEEE Elec. Dev. Lett, Vol.26, No.2, 2005, pp.87-89

Jun Yuan, Jason C. S. Woo, "A Novel Split Gate MOSFET Design Realized By a Fully Silicided Gate Process for the Improvement of Trans-conductance and Output Resistance", to be published in IEEE Elec. Dev. Lett, 2005.

2004

Suryagandh, S.S., Garg, M., Woo, J.C.S. "A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs," IEEE Transactions on Electron Devices, vol.51, no.7, July 2004, pp.1122-28. Publisher: IEEE, USA.

Seong-Dong Kim, Wada, H., Woo, J.C.S. "TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling," IEEE Transactions on Semiconductor Manufacturing, vol.17, no.2, May 2004, pp.192-200. Publisher: IEEE, USA.

Jun Yuan, Jason C. S. Woo "Nanoscale MOSFET With Split-Gate Design for RF/Analog Application," Japanese Journal of Applied Physics, vol.43, no.4B, 2004.

2002

Seong-Dong Kim, Cheol-Min Park, Woo JCS. "Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS," IEEE Transactions on Electron Devices, vol.49, no.10, Oct. 2002, pp.1748-54. Publisher: IEEE, USA.

Deshpande HV, Baohong Cheng, Woo JCS. "Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications," IEEE Transactions on Electron Devices, vol.49, no.9, Sept. 2002, pp.1558-65. Publisher: IEEE, USA.

Borse DG, Rani KN M, Jha NK, Chandorkar AN, Vasi J, Ramgopal Rao V, Cheng B, Woo J. C .S. "Optimization and realization of sub-100-nm channel length single halo p-MOSFETs," [Journal Paper] IEEE Transactions on Electron Devices, vol.49, no.6, June 2002, pp.1077-9. Publisher: IEEE, USA.

Najeev-ud-din, Dunga MV, Kumar A, Vasi J, Ramgopal Rao V, Baohong Cheng, Woo JCS. "Analysis of floating body effects in thin film conventional and single pocket SOI MOSFETs using the GIDL current technique," IEEE Electron Device Letters, vol.23, no.4, April 2002, pp.209-11. Publisher: IEEE, USA.

Seong-Dong Kim, Cheol-Min Park, Woo JCS. "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis," IEEE Transactions on Electron Devices, vol.49, no.3, March 2002, pp.467-72. Publisher: IEEE, USA.

Seong-Dong Kim, Cheol-Min Park, Woo JCS. "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation," IEEE Transactions on Electron Devices, vol.49, no.3, March 2002, pp.457-66. Publisher: IEEE, USA.

2001

Ying-Che Tseng; Huang, W.M.; Mendicino, M.; Monk, D.J.; Welch, P.J.; Woo, J.C.S.; "Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs" Electron Devices, IEEE Transactions on , Volume: 48 Issue: 7 , Jul 2001 Page(s): 1428 -1437

Mahapatra, S.; Rao, V.R.; Cheng, B.; Khare, M.; Parikh, C.D.; Woo, J.C.S.; Vasi, J.M.; "Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si3N4 MOSFETs," Electron Devices, IEEE Transactions on , Volume: 48 Issue: 4 , Apr 2001 Page(s): 679 -684

2000

Y.-C. Tseng, W.M. Huang, C. Hwang, and J.C.S. Woo, "AC Floating Body Effects in Partially Depleted Floating Body SOI nMOS Operated at ElevatedTemperature: an Analog Circuit Prospective," IEEE Transactions on Electron Devices, pp. 494-496, October 2000.

1999

Anand Inani, Ramgopal Valipe Rao, Baohong Cheng and Jason Woo, "Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs," Japanese Journal of Applied Physics, Vol.38, 1999, pp. 2266-2271.

B. Cheng, V.R. Rao and J.C.S. Woo, "Exploration of Velocity Overshoot in a High-performance Deep Sub-0.1mm SOI MOSFET with Asymmetric Channel Profile," IEEE Transactions on Electron Devices, pp. 538-540, October 1999.

Y.-C. Tseng, W.M. Huang, V. Ilderem, and J.C.S. Woo, "Floating Body Induced Pre-kink Excess Low-frequency Noise in Submicron SOI CMOSFET Technology," IEEE Electron Device Letters, pp. 484-486, September 1999.

Y.-C. Tseng, W.M. Huang, D.J Monk, P. Welch, J.M. Ford, and J.C.S. Woo, "AC Floating Body Effects and the Resultant Analog Circuit Issues in submicron Floating Body and Body-grounded SOI MOSFETs," IEEE Transactions on Electron Devices, pp. 1685-1692, August 1999.

B. Cheng, M Cao, P.V. Voorde, W. Greene, H. Stork, Z. Yu, and J.C.S. Woo, "The Impact of High-K Gate Dielectrics on Sub-0.1 mm MOSFETs Design," IEEE Transactions on Electron Devices, pp. 1537-1544, July 1999.

B. Cheng, M. Cao, P.V. Voorde, W. Greene, H. Stork, Z. Yu, and J.C.S. Woo, "Design consideration of high-K Gate Dielectrics for sub-0.1mm MOSFET's," IEEE Transactions on Electron Devices, pp. 261-262, January 1999.

Y.-C. Tseng, W.M. Huang, E. Spears, D. Spooner, D. Ngo, J.M. Ford, and J.C.S. Woo, "Phase Noise Characteristics Associated with Low-frequency Noise in Sub-micron SOI MOSFET Feedback Oscillator for RF IC's," IEEE Electron Device Letters, pp. 54-56, January 1999.

1998

Y.-C. Tseng, W.M. Huang, D. Diaz, J.M. Ford, and J.C.S. Woo, "AC Floating Body Effects in Submicron Fully-Depleted (FD) SOI nMOSFETs and the Impact on Analog Applications," IEEE Electron Device Letters, pp. 351-353, September 1998.

P. Liu, T.C. Hsiao, and J.C.S. Woo, "A Low Thermal Budget Self-Aligned Ti Silicide Technology Using Germanium Implantation for Thin-Film SOI MOSFET's," IEEE Transactions on Electron Devices, pp. 1280-1286, June 1998.

T.C. Hsiao, P. Liu, and J.C.S. Woo, "Advanced Technologies for Optimized Sub-Quarter-Micrometer SOI CMOS Devices," IEEE Transactions on Electron Devices, pp. 1092-1098, May 1998.

Y.C. Tseng, W.M. Huang, P. Welch, J. Ford, and J.C.S. Woo, "Empirical Correlation Between AC Kink and Low-Frequency Noise Overshoot in SOI MOSFETs," IEEE Electron Device Letters, pp. 157-159, May 1998.

1997

T.C. Hsiao, P. Liu, and J.C.S. Woo, "An Advanced Ge Preamorphization Salicide Technology for Ultra-Thin-Film SOI CMOS Devices," IEEE Electron Device Letters, pages 309-311, July 1997.

V.M. Chen and J.C.S. Woo, "Tunneling Source-Body Contact for Partially-Depleted SOI MOSFET," IEEE Transactions on Electron Devices,pp. 1143-1147, July 1997.

F. Deng, R. Johnson, P. Asbeck, S. Lau, W. Dubbelday, T. Hsiao, and J.C.S. Woo, "Salicidation Process using NiSi and Its Device Application," Journal of Applied Physics, pp. 8047-8051, June 1997.

M. Song, K.P. MacWilliams, and J.C.S. Woo, "Comparison of NMOS and PMOS Hot Carrier Effects From 300 K to 77 K," IEEE Transactions on Electron Devices, pages 268-276, February 1997.

B. Cheng and J.C.S. Woo, "A Temperature-Dependent MOSFET Inversion Layer Carrier Mobility Model for Device and Circuit Simulation," IEEE Transactions on Electron Devices, pp. 343-345, February 1997.

J. Seo, J.C.S. Woo, M. Mendicino, and P. Vasudev, "An Advanced Ge Pre-Amorphization Salicide Technology for Sub-Quarter Micrometer SOI CMOS Devices," Symposium on VLSI Technology, Digest of Technical Papers, pp. 95-96, June 1997.

1996

N. Kistler and J.C.S. Woo, "Scaling Behavior of Sub-Micron MOSFETs on Fully Depleted SOI," Solid-State Electronics, pp. 445-454, April 1996.

D.K. Nayak, J.C.S. Woo, J.S. Park, K.L. Wang, and K.P. MacWilliams, "Hole Confinement in a Si/GeSi/Si Quantum Well on SIMOX," IEEE Transactions on Electron Devices, pp. 180-182, January 1996.

1995

C.Y. Hwang, T.C. Kuo, and J.C.S Woo, "Extraction of Gate Dependent Source/Drain Resistance and Effective Channel Length in MOS Devices at 77 K," IEEE Transactions on Electron Devices, pp. 1863-1865, October 1995.

J. Wang-Ratkovic, W.M. Huang, B.Y. Hwang, M. Racanelli, J. Foerstner, and J.C.S. Woo, "Lifetime Reliability of Thin-Film SOI nMOSFETs," IEEE Electron Device Letters, pp. 387-389, September 1995.

C.H. Lin, J. Cable, and J.C.S. Woo, "Temperature and Electric Field Characteristics of Time-Dependent Dielectric Breakdown for Silicon Dioxide and Reoxidized-Nitrided Oxides," IEEE Transactions on Electron Devices, pp. 1329-1332, July 1995.

T.C. Hsiao, and J.C.S. Woo, "Subthreshold Characteristics of Fully Depleted Submicrometer SOI MOSFET's," IEEE Transactions on Electron Devices, pp. 1120-1125, June 1995.

1994

D. Nayak, J.C.S. Woo, J. Park, K.L. Wang, and K. MacWilliams, "High-Mobility P-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor on Strained Si," Japanese Journal of Applied Physics, pp. 2412-2414, April 1994.

J. Wang, J.C.S. Woo, and C.R. Viswanathan, "Mobility-Field Behavior of Fully Depleted SOI MOSFETs," IEEE Electron Device Letters, pp. 117-119, April 1994.

T.C. Hsiao, N. Kistler, and J.C.S. Woo, "Modeling the I-V Characteristics of Fully Depleted Submicrometer SOI MOSFET's," IEEE Electron Device Letters, pp. 45-47, February 1994.

1992

N. Kistler, E. Ver Ploeg, J.C.S. Woo, and J. Plummer, "Sub-Quarter Micron CMOS on Ultra-Thin (400 A) SOI," IEEE Electron Device Letters, pp. 235-237, 1992.

D. Nayak, K. Kamjoo, J.C.S. Woo, J. Park, and K.L. Wang, "Rapid Isothermal Processing of Strained GeSi Layers," IEEE Transactions on Electron Devices, pages 56-63, 1992.

J.S. Cable and J.C.S. Woo, "High Field Mobility Effects in ONO Transistors," IEEE Transactions on Electron Devices, pp. 607-613, 1992.

1991

N. Kistler, J.C.S. Woo, C.R. Viswanathan, K. Terrill, and P.K. Vasudev, "Substrate Current Measurements in Thin SOI MOSFET's at 300K and 77K," IEEE Transactions on Electron Devices, pp. 2684-2686, 1991.

J.S. Cable and J.C.S. Woo, "Hot-Carrier Induced Interface State Generation in Submicron Transistors at 77K," IEEE Transactions on Electron Devices, pp. 2612-2618, 1991.

J. Chang, D. Nayak, V.K. Raman, J.C.S. Woo, J. Park, K.L. Wang, and C.R. Viswanathan, "Low Frequency Noise in Quantum-Well Ge{x}Si{1-x} pMOSFET's," Microelectronic Engineering, Volume 15, pp. 19-22, 1991.

M. Song, J.S. Cable, K.P. MacWilliams, and J.C.S. Woo, "Optimization of LDD Devices for Cryogenic Operation," IEEE Electron Device Letters, pp. 375-378, 1991.

J. Wang, N. Kistler, J.C.S. Woo, and C.R. Viswanathan, "Threshold Voltage Instability at Low Temperatures in Partially Depleted Thin Film SOI MOSFET's," IEEE Electron Device Letters, pp. 300-302, 1991.

K. Kamjoo, D. Nayak, J. Park, J.C.S. Woo, and K.L. Wang, "Study of Si/GeSi P-N Heterostructures," Journal of Applied Physics, pp. 6674-6678, 1991.

D. Nayak, J. Woo, K.L. Wang, and K.P. MacWilliams, "Enhancement-mode Quantum-Well Ge{x}Si{1-x} PMOS," IEEE Electron Device Letters, pp. 154-156, 1991.

J.S. Cable, R.A. Mann, and J.C.S. Woo, "Impurity Barrier Properties of Reoxidized Nitrided Oxide Films for Use With p+-doped Polysilicon Gates," IEEE Electron Device Letters, pp. 128-130, 1991.

1990

D. Nayak, K. Kamjoo, J. Woo, J. Park, and K.L. Wang, "Wet Oxidation of GeSi Strained Layers by Rapid Thermal Processing," Applied Physics Letters, pp. 369-371, 1990.

S.J. Chang, V. Arbet, K.L. Wang, R.C. Bowman, P.M. Adams, D. Nayak, and J.C.S. Woo, "Studies of interdiffusion in Ge{m}Si{n} Strained Layer Supperlattices," Journal of Electronic Materials, pp. 125-129, 1990.

D. Nayak, K. Kamjoo, J. Woo, J. Park, and K.L. Wang, "Rapid Thermal Oxidation of GeSi Strained Layers," Applied Physics Letters, pp. 66-68, 1990.