JOURNAL ARTICLES | |
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[J41] | W. Romaszkan, T. Li, R. Garg, J. Yang, S. Pamarti and P. Gupta, "A 4.4-75-TOPS/W 14-nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator," in IEEE Solid-State Circuits Letters, vol. 5, pp. 206-209, 2022. [link] |

[J40] | S. Bu and S. Pamarti, "A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation," in IEEE Journal of Solid-State Circuits, vol. 57, no. 5, pp. 1457-1469, May 2022. [link] |

[J39] | S. Bu, S. Hameed and S. Pamarti, "Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends," in IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 928-939, March 2021. [link] |

[J38] | H. Esmaeelzadeh and S. Pamarti, "A sub-nW 32-kHz crystal oscillator architecture based on a DC-only sustaining amplifier," IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3247-3256, Dec. 2019. [link] |

[J37] | S. Hameed and S. Pamarti, "Design and analysis of a programmable receiver front end with time-interleaved baseband analog-FIR filtering," IEEE Journal of Solid-State Circuits, vol. 53, no. 11, pp. 3197-3207, Nov. 2018. [link] |

[J36] | S. Hameed and S. Pamarti, "Impedance matching and reradiation in LPTV receiver front-ends: An analysis using conversion matrices," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 65, no. 9, pp. 2842-2855, Sep. 2018. |

[J35] | J. Lee, R. Gomez, and S. Pamarti, "A broadband class-AB power amplifier with instantaneous supply-switching efficiency enhancement for cable TV application," IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 762-771, Mar. 2018. |

[J34] | S. Hameed and S. Pamarti, "Design and analysis of a programmable receiver front end based on baseband analog-FIR filtering using an LPTV resistor," IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1592-1606, June 2018. |

[J33] | N. Sinha and S. Pamarti, "Theoretical analysis of circuit non-idealities in a passive spectrum scanner based on periodically time-varying circuit components," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 65, no. 8, pp. 2403-2410, Aug. 2018. |

[J32] | H. Esmaeelzadeh and S. Pamarti, "A quick startup technique for high-Q oscillators using precisely timed energy injection," IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 692-702, Mar. 2018. |

[J31] | N. Nidhi and S. Pamarti, "Design and analysis of a 1.8-GHz open-loop modulator for phase modulation and frequency synthesis using TDC-based calibration," IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 10, pp. 3975-3988, Oct. 2017. |

[J30] | N. Sinha, M. Rachid, S. Pavan, and S. Pamarti, "Design and analysis of an 8 mW, 1 GHz span, passive spectrum scanner with >+31dBm out-of-band IIP3 using periodically time-varying circuit components," IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2009-2025, Aug. 2017. |

[J29] | M. Nariman, F. Shirinfar, S. Pamarti, A. Rofougaran, and F. De Flaviis, "High efficiency mm-wave energy harvesting systems with milliwatt-level output power," IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 64, no. 6, pp. 605-609, June 2017. |

[J28] | Y. Ismail, H. Lee, S. Pamarti, and C.-K. K. Yang, "A 36-V 49% efficient hybrid charge pump in nanometer-scale bulk CMOS technology," IEEE Journal of Solid-State Circuits, vol. 52, no. 3, pp. 781-798, Mar. 2017. |

[J27] | M. H. Roshan, S. Zaliasl, K. Joo, K. Souri, R. Palwai, L. Chen, A. Singh, S. Pamarti, N. Miller, J. C. Doll, C. Arft, S. Tabatabaei, C. Sechen, A. Partridge, and V. Menon, "A MEMS-assisted temperature sensor with 20-uK resolution, conversion rate of 200 S/s, and FOM of 0.04 pJK^2," IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 185-197, Jan. 2017. |

[J26] | M. Nariman, F. Shirinfar, A. P. Toda, S. Pamarti, A. Rofougaran, and F. De Flaviis, "A compact 60-GHz wireless power transfer system," IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 8, pp. 2664-2677, Aug. 2016. |

[J25] | S. Hameed, M. Rachid, B. Daneshrad, and S. Pamarti, "Frequency-domain analysis of N-path filters using conversion matrices," IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 63, no. 1, pp. 74-78, Jan. 2016. |

[J24] | A. Ghosh and S. Pamarti, "Linearization through dithering: A 50 MHz bandwidth, 10-b ENOB, 8.2 mW VCO-based ADC," IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2012-2024, Sep. 2015. |

[J23] | S. Zaliasl, J. C. Salvia, G. C. Hill, L. Chen, K. Joo, R. Palwai, N. Arumugam, M. Phadke, S. Mukherjee, H.-C. Lee, C. Grosjean, P. M. Hagelin, S. Pamarti, T. S. Fiez, K. A. A. Makinwa, A. Partridge, and V. Menon, "A 3 ppm 1.5?.8 mm^2 1.0 uA 32.768 kHz MEMS-based oscillator," IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 291-302, Jan. 2015. |

[J22] | M. Song, I. Jung, S. Pamarti and C. Kim, "A 2.4 GHz 0.1-Fref-bandwidth all-digital phase-locked loop with delay-cell-less TDC," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 60, no. 12, pp. 3145-3151, Dec. 2013. |

[J21] | M. Rachid, S. Pamarti, and B. Daneshrad, "Filtering by aliasing," IEEE Transactions on Signal Processing, vol. 61, no. 9, pp. 2319-2327, May 2013. |

[J20] | M. H. Perrott, J. C. Salvia, F. S. Lee, A. Partridge, S. Mukherjee, C. Arft, J. Kim, N. Arumugam, P. Gupta, S. Tabatabaei, S. Pamarti, H. Lee, and F. Assaderaghi, "A temperature-to-digital converter for a MEMS-based programmable oscillator with <+/-0.5-ppm frequency stability and <1-ps integrated jitter," IEEE Journal of Solid-State Circuits, vol. 48, no. 1, pp. 276-291, Jan. 2013. |

[J19] | N. Singhal, H. Zhang, and S. Pamarti, "A zero-voltage-switching contour-based outphasing power amplifier," IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 6, pp. 1896-1906, June 2012. |

[J18] | W. Yao, Y. Shi, L. He, and S. Pamarti, "Worst-case estimation for data-dependent timing jitter and amplitude noise in high-speed differential link," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 1, pp. 89-97, Jan. 2012 |

[J17] | B. Fitzgibbon, S. Pamarti, and M. P. Kennedy, "A spur-free MASH DDSM with high-order filtered dither," IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 58, no. 9, pp. 585-589, Sep. 2011. |

[J16] | N. Singhal, N. Nidhi, R. Patel, and S. Pamarti, "A zero-voltage-switching contour-based power amplifier with minimal efficiency degradation under back-off," IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 6, pp. 1589-1598, June 2011. |

[J15] | P.-E. Su and S. Pamarti, "A 2.4 GHz wideband ppen-loop GFSK transmitter with phase quantization noise cancellation," IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 615-626, Mar. 2011. |

[J14] | M. H. Perrott, S. Pamarti, E. G. Hoffman, F. S. Lee, S. Mukherjee, C. Lee, V. Tsinker, S. Perumal, B. T. Soto, N. Arumugam, and B. W. Garlepp, "A low area, switched-resistor based fractional-N synthesizer applied to a MEMS-based programmable oscillator," IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2566-2581, Dec. 2010. |

[J13] | T.-C. Hsueh, P.-E. Su, and S. Pamarti , "A 3?.8 Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation," IEEE Journal of Solid-State Circuits, vol. 45, no. 8, pp. 1522-1532, Aug. 2010. |

[J12] | P.-E. Su and S. Pamarti, "Mismatch shaping techniques to linearize charge pump errors in fractional-N PLLs," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 57, no. 6, pp. 1221-1230, June 2010. |

[J11] | N. Singhal and S. Pamarti, "A digital envelope combiner for switching power amplifier linearization," IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 57, no. 4, pp. 270-274, Apr. 2010. |

[J10] | P.-E. Su and S. Pamarti, "Fractional-N phase-locked-loop-based frequency synthesis: A tutorial," IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 56, no. 12, pp. 881-885, Dec. 2009. |

[J9] | S. Pamarti, "Digital techniques for integrated frequency synthesizers: A tutorial," IEEE Communications Magazine, vol. 47, no. 4, pp. 126-133, Apr. 2009. |

[J8] | S. Pamarti and S. Delshadpour, "A spur elimination technique for phase interpolation-based fractional-N PLLs," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 55, no. 6, pp. 1639-1647, Jul. 2008. |

[J7] | S. Pamarti, "A theoretical study of the quantization noise in split Delta-Sigma ADCs," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 55, no. 5, pp. 1267-1278, June 2008. |

[J6] | S. Pamarti , "The effect of noise cross-coupling on time-interleaved Delta-Sigma ADCs," IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 55, no. 6, pp. 532-536, June 2008. |

[J5] | S. Pamarti and I. Galton, "LSB dithering in MASH Delta-Sigma D/A converters," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 54, no. 4, pp. 779-790, Apr. 2007. |

[J4] | S. Pamarti, J. Welz, and I. Galton, "Statistics of the quantization noise in 1-nit dithered single-quantizer digital Delta-Sigma modulators," IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 54, no. 3, pp. 492-503, Mar. 2007. |

[J3] | E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, "Replica compensated linear regulators for supply-regulated phase-locked loops," IEEE Journal of Solid-State Circuits, vol. 41, no. 2, pp. 413-424, Feb. 2006. |

[J2] | S. Pamarti, L. Jansson, and I. Galton, "A wideband 2.4-GHz Delta-Sigma fractional-N PLL with 1-Mb/s in-loop modulation," IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 49-62, Jan. 2004. |

[J1] | S. Pamarti and I. Galton, "Phase-noise cancellation design tradeoffs in Delta-Sigma fractional-N PLLs," IEEE Transactions on Circuits and Systems II, Analog and Digital Signal Processing, vol. 50, no. 11, pp. 829-838, Nov. 2003. |

CONFERENCE PAPERS | |

[C64] | J. Yang, T. Li, W. Romaszkan, P. Gupta and S. Pamarti, "A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor," 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), Taipei, Taiwan, 2022, pp. 10-11. [link] |

[C63] | J. Song, L. -Y. Chen, M. -C. F. Chang, S. Pamarti and C. -K. K. Yang, "A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2047-2051. [link] |

[C62] | S. Bu, V. K. Jacob and S. Pamarti, "A Digital Alias Cancellation Technique for Filtering-by-Aliasing Receivers," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 232-233. [link] |

[C61] | S. Pal et al., "Designing a 2048-Chiplet, 14336-Core Waferscale Processor," 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2021, pp. 1183-1188. [link] |

[C60] | Y. Zhang et al., "J. Yang et al., "A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM," ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), Grenoble, France, 2021, pp. 115-118. [link] |

[C59] | Y. Zhang et al., "A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS," ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), Grenoble, France, 2021, pp. 435-438 [link] |

[C58] | S. Pal et al., "I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, pp. 298-303. [link] |

[C57] | S. Bu and S. Pamarti, "A 0.9V dual-channel filtering-by-aliasing receiver front-end achieving +35dBm IIP3 and <-81dBm LO leakage supporting intra- and inter-band carrier aggregation," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2021. [link] |

[C56] | T. Li, W. Romaszkan, S. Pamarti, and P. Gupta, "GEO: generation and execution optimized stochastic computing accelerator for neural networks," in Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), Feb. 2021, accepted. |

[C55] | W. Romaszkan, T. Li, T. Melton, S. Pamarti, and P. Gupta, "ACOUSTIC: accelerating convolutional neural networks through or-unipolar skipped stochastic computing," in Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, France, Mar. 2020, pp. 768-773. |

[C54] | M. Elhebeary, L.-Y. Chen, S. Pamarti, and C.-K. K. Yang, "An 8.5pJ/bit ultra-low power wake-up receiver using Schottky diodes for IoT Applications," in Proceedings of IEEE European Solid-State Circuits Conference (ESSCIRC), Cracow, Poland, Sep. 2019, pp. 205-208. |

[C53] | S. Bu, S. Hameed and S. Pamarti, "An LPTV noise cancellation technique for a 0.9-V filtering-by-aliasing receiver front-end with >67-dB stopband rejection," in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr. 2019, pp. 1-4. |

[C52] | H. Esmaeelzadeh and S. Pamarti, "A 0.55nW/0.5V 32kHz crystal oscillator based on a DC-only sustaining amplifier for IoT," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2019, pp. 300-301. |

[C51] | S.-Y. Hung and S. Pamarti, "A 0.5-2.5 GHz multi-output fractional frequency synthesizer with 90fs jitter and -106dBc spurious tones based on digital spur cancellation", in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2019, pp. 262-263. |

[C50] | S. Jangam, S. Pal, A. Bajwa, S. Pamarti, P. Gupta, and S. S. Iyer, "Latency, bandwidth and power benefits of the SuperCHIPS integration scheme," in Proceedings of IEEE Electronic Components and Technology Conference (ECTC), Orlando, FL, May-June 2017, pp.86-94. |

[C49] | J. Lee, S. Pamarti, and R. A. Gomez, "Training of digital predistortion based on signal-to-distortion-ratio measurements," in Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Miami, FL, Oct. 2017, pp. 9-12. |

[C48] | H. Esmaeelzadeh and S. Pamarti, "A precisely-timed energy injection technique achieving 58/10/2?s start-up in 1.84/10/50MHz crystal oscillators," in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr.-May 2017, pp.1-4. |

[C47] | J. Lee, S. Pamarti, and R. Gomez, "A 10-to-650MHz 1.35W class-AB power amplifier with instantaneous supply-switching efficiency enhancement," in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr.-May 2017, pp.1-4. |

[C46] | F. Shirinfar, R. Rofoufaran, and S. Pamarti, "Adaptive gain and phase adjustment for local linearization of power amplifiers of micro/mm-wave phase arrays," in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, June 2017, pp. 224-227. |

[C45] | S. Hameed and S. Pamarti, "A time-interleaved filtering-by-aliasing receiver front-end achieving >70dB suppression at <4?bandwidth frequency offset," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2017, pp. 418-419 |

[C44] | S. Pamarti, N. Sinha, S. Hameed, and M. Rachid, "Time-varying circuit approaches for software defined and cognitive radio applications," in Proceedings of IEEE International SoC Design Conference (ISOCC), Jeju, South Korea, Oct. 2016, pp. 155-156. |

[C43] | W. Wu, Y.-L. Chen, Y. Ma, C.-N. J. Liu, J.-Y. Jou, S. Pamarti, and L. He, "Wave digital filter based analog circuit emulation on FPGA," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1286-1289. |

[C42] | N. Sinha, M. Rachid, and S. Pamarti, "An 8mW, 1GHz span, passive spectrum scanner with > +31dBm out-of-band IIP3," in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, May 2016, pp.278-281. |

[C41] | S. Hameed, N. Sinha, M. Rachid, and S. Pamarti, "A programmable receiver front-end achieving >17dBm IIP3 at <1.25?BW frequency offset," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Jan.-Feb. 2016, pp.446-447. |

[C40] | M. H. Roshan, S. Zaliasl, K. Joo, K. Souri, R. Palwai, W. Chen, S. Pamarti, J. C. Doll, N. Miller, C. Arft, S. Tabatabaei, C. Sechen, A. Partridge, and V. Menon, "Dual-MEMS-Resonator temperature-to-digital converter with 40uK resolution and FOM of 0.12pJK^2," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Jan.-Feb. 2016, pp. 200-201. |

[C39] | N. Sinha,M. Rachid, and S. Pamarti, "A sharp programmable passive filter based on filtering by aliasing," in Proceedings of IEEE Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan, June 2015, pp. C58-C59. |

[C38] | S. Hameed, M. Rachid, B. Daneshrad, and S. Pamarti, "Frequency-domain analysis of a mixer-first receiver using conversion matrices," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp.541-544. |

[C37] | N. Nidhi and S. Pamarti, "A 1.8GHz wideband open-loop phase modulator with TDC based non-linearity calibration in 0.13?m CMOS," in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Phoenix, AZ, May 2015, pp. 91-94. |

[C36] | S. Shim and S. Pamarti, "A 1.85GHz CMOS power amplifier with zero-voltage-switching contour-based outphasing control to improve back-off efficiency," in Proceedings of IEEE MTT-S International Microwave Symposium (IMS), Phoenix, AZ, May 2015, pp. 1-4. |

[C35] | H. Parta, M. D. Ercegovac, and S. Pamarti, "RF digital predistorter implementation using polynomial optimization," in Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, TX, Aug. 2014, pp. 981-984. |

[C34] | S. Hameed, J. Shin, M.-C. F. Chang, and S. Pamarti, "A 9.8-bit ENOB 1.25 GHz open-loop phase modulator," in Proceedings of Government Microcircuit Applications & Critical Technology (GOMACTech) Conference, Charleston, SC, Mar.-Apr. 2014, pp. 211-215. |

[C33] | Y. Ismail, H. Lee, S. Pamarti, and C.-K. K. Yang, "A 34V charge pump in 65nm bulk CMOS technology," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2014, pp. 408-409. |

[C32] | S. Z. Asl, S. Mukherjee, W. Chen, K. Joo, R. Palwai, N. Arumugam, P. Galle, M. Phadke, C. Grosjean, J. Salvia, H. Lee, S. Pamarti, T. Fiez, K. Makinwa, A. Partridge, and V. Menon, "A 1.55?.85mm^2 3ppm 1.0?A 32.768kHz MEMS-based oscillator," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2014, pp. 226-227. |

[C31] | A. Ghosh, and S. Pamarti, "A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization," in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, Sep. 2013, pp. 1-4. |

[C30] | A. Ghosh, and S. Pamarti, "Enabling high-speed, high-resolution ADCs using signal conditioning algorithms," in Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, Aug. 2013, pp. 856-859. |

[C29] | A. Ghosh and S. Pamarti, "Adaptive signal conditioning algorithms to enable wideband signal digitization," in Proceedings of IEEE International Conference on Communications (ICC), Budapest, Hungary, June 2013, pp. 4566-4570. |

[C28] | M. Nariman, F. Shirinfar, S. Pamarti, M. Rofougaran, R. Rofougaran, and F. De Flaviis, "A compact millimeter-wave energy transmission system for wireless applications," in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, WA, June 2013, pp. 407-410. |

[C27] | F. Shirinfar, M. Nariman, T. Sowlati, M. Rofougaran, R. Rofougaran, and S. Pamarti, "A fully integrated 22.6dBm mm-Wave PA in 40nm CMOS," in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, WA, June 2013, pp. 279-282. |

[C26] | F. Shirinfar, M. Nariman, T. Sowlati, M. Rofougaran, R. Rofougaran, and S. Pamarti, "A multichannel, multicore mm-Wave clustered VCO with phase noise, tuning range, and lifetime reliability enhancements," in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, WA, June 2013, pp. 235-238. |

[C25] | A. Ghosh and S. Pamarti, "Filtering of subtractive discrete dither in quantizers: Some new results," in Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Vancouver, Canada, May 2013, pp. 5790-5794. |

[C24] | A. Ghosh and S. Pamarti, "Mitigating timing errors in time-interleaved ADCs: A signal conditioning approach," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 2013, pp. 357-360. |

[C23] | N. Singhal, S. Shim, and S. Pamarti, "Class-E PA efficiency enhancement using zero voltage switching contour control," in Proceedings of IEEE Annual Conference on Wireless and Microwave Technology (WAMICON), Orlando, FL, Apr. 2013, pp. 1-6. |

[C22] | J. Shin, S. Hameed, Q. J. Gu, M.-C. F. Chang, and S. Pamarti, "A wide bandwidth open-loop phase modulator," in Proceedings of Government Microcircuit Applications & Critical Technology (GOMACTech) Conference, Las Vegas, NV, Mar. 2013. |

[C21] | M. Yu, S. Suko, M. Fitelson, S. Pamarti, and Q. J. Gu, "Recent development progress of an X-band high efficiency transmitter using class E PA and split-band supply modulation," in Proceedings of Government Microcircuit Applications & Critical Technology (GOMACTech) Conference, Las Vegas, NV, Mar. 2013. |

[C20] | N. Singhal, R. Patel, and S. Pamarti, "A 25 dBm parallel class E power amplifier with minimal efficiency degradation under 10 dB back-off", in IEEE MTT-S International Microwave Symposium (IMS) Digest, Montreal, Canada, June 2012, pp. 1-3. |

[C19] | C. Choudhuri, A. Ghosh, U. Mitra, and S. Pamarti, "Robustness of xampling-based RF receivers against analog mismatches," in Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Kyoto, Japan, Mar. 2012, pp. 2965-2968. |

[C18] | M. Perrott, J. Salvia, F. Lee, A. Partridge, S. Mukherjee, C. Arft, J.-T. Kim, N. Arumugam, P. Gupta, S. Tabatabaei, S. Pamarti, H. Lee, and F. Assaderaghi, "A temperature-to-digital converter for a MEMS-based programmable oscillator with better than +/-0.5ppm frequency stability," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2012, pp. 206-208. |

[C17] | N. Nidhi, P.-E. Su, and S. Pamarti, "Open loop modulation techniques for wide bandwidth digital frequency synthesis," in Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, South Korea, Aug. 2011, pp. 1-4. |

[C16] | A. Ghosh and S. Pamarti, "A novel quantization noise-cancellation scheme in wideband D/A converters," in Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, South Korea, Aug. 2011, pp. 1-4. |

[C15] | F. S. Lee, J. Salvia, C. Lee, S. Mukherjee, R. Melamud, N. Arumugam, S. Pamarti, C. Arft, P. Gupta, S. Tabatabaei, B. Garlepp, H.-C. Lee, A. Partridge, M. H. Perrott, and F. Assaderaghi, "A programmable MEMS-based clock generator with sub-ps jitter performance," in Proceedings of IEEE Symposium on VLSI Circuits (VLSIC), Honolulu, HI, June 2011, pp. 158-159. |

[C14] | N. Singhal, N. Nidhi, A. Ghosh, and S. Pamarti, "A 19 dBm 0.13um CMOS parallel class-E switching PA with minimal efficiency degradation under 6 dB back-off," in IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Digest of Papers, Baltimore, MD, June 2011, pp. 1-4. |

[C13] | S. D'Souza, F. Chang, S. Pamarti, B. Agarwal, H. Zarei, T. Sowlati, and R. Berenguer, "A progammable baseband anti-alias filter for a passive-mixer-based, SAW-less, multi-band, multi-mode WEDGE transmitter," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 2011, pp. 450-453. |

[C12] | M. Rachid, S. Pamarti, and B. Daneshrad, "A novel reconfigurable alias interference cancellation technique for A-to-D conversion," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 2011, pp. 1656-1659. |

[C11] | T.-C. Hsueh and S. Pamarti, "A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment," in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, Sep. 2010, pp. 1-4. |

[C10] | N. Singhal, N. Nidhi, and S. Pamarti, "A power amplifier with minimal efficiency degradation under back-off," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, June 2010, pp. 1851-1854. |

[C9] | P.-E. Su and S. Pamarti, "A 2-MHz bandwidth Delta-Sigma fractional-N synthesizer based on a fractional frequency divider with digital spur suppression," in Proceedings of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Anaheim, CA, May 2010, pp. 413-416. |

[C8] | M. H. Perrott, S. Pamarti, E. Hoffman, F. S. Lee, S. Mukherjee, C. Lee, V. Tsinker, S. Perumal, B. Soto, N. Arumugam, and B. W. Garlepp, "A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2010, pp. 244-245. |

[C7] | W. Yao, Y. Shi, L. He, and S. Pamarti, "Joint design-time and post-silicon optimization for digitally tuned analog circuits," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Digest of Technical Papers, San Jose, CA, Nov. 2009, pp. 725-730. |

[C6] | T.-C. Hsueh, P.-E. Su, and S. Pamarti, "A 3?.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation," in Proceedings of IEEE Custom Integrated Circuits Conference, Rome, Italy, Sep. 2009, pp. 121-124. |

[C5] | W. Yao, Y. Shi, L. He, S. Pamarti, and Y. Hu, "Worst case timing jitter and amplitude noise in differential signaling," in Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, Mar. 2009, pp. 40-46. |

[C4] | S. Farshchi, D. Markovic, S. Pamarti, B. Razavi, amd J. W. Judy, "Towards neuromote: A single-chip, 100-channel, neural-signal acquisition, processing, and telemetry device," in Proceedings of Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Lyon, France, Aug. 2007, pp. 437-440. |

[C3] | S. Pamarti, "A theoretical analysis of split Delta-Sigma ADCs," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, LA, May 2007, pp. 493-496. |

[C2] | C. Long, S. Reddy, S. Pamarti, L. He, T. Karnik, "Power-efficient pulse width modulation DC/DC converters with zero voltage switching control," in Proceedings of IEEE International Symposium on Low Power Electronics and Design (ISLPED), Tegernsee, Germany, Oct. 2006, pp. 326-329. |

[C1] | K. Chang, S. Pamarti, K. Kaviani, E. Alon, X. Shi, T. J. Chin, J. Shen, G. Yip, C. Madden, R. Schmitt, C. Yuan, F. Assaderaghi, and M. Horowitz, "Clocking and circuit design for a parallel I/O on a first-generation CELL processor," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, Feb. 2005, pp. 526-615. |