Open Loop Frequency Synthesizer with Digital Spur Cancellation

In large System on Chips (SoCs), low jitter clock signals at multiple different frequencies need to be generated on chip using low power and small area. The conventional PLL-based frequency synthesizer suffers from large area and high power consumption because it needs a local oscillator for every frequency it generates. The open loop digital solution based on Digital-to-Phase Converters (DPCs) get rid of the need for multiple local oscillators. However, the circuit mismatches create strong spurious tones that degrades the quality of the signal.

This project explores a new, purely digital spur cancellation technique that uses a bang-bang phase detector (BBPD) and a dithered noisy but mostly spur-free auxiliary clock generator to extract spurious tones, and digitally corrects for them. When applied to a DPC-based frequency synthesizer it achieves integrated jitter <90fs and spurious tones < -106dBc on a 2.48 GHz carrier. The spurious tones level is 33dB better than the best in prior art.


[1] Szu-Yao Hung and Sudhakar Pamarti, "A 0.5-2.5 GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation", IEEE International Solid-State Circuits Conference (ISSCC), pp 262~263, 2019.

Sharp Programmable Anti-Alias Filter Using LPTV Circuits

As communications technology migrates towards wideband software-defined radios (SDR) and cognitive radios (CR), receivers are expected to dynamically acquire or monitor one or more signals of interest whose frequency locations, bandwidths, and interference scenarios may not be known apriori. Off-chip filters (e.g., SAW filters), which are employed in traditional receivers, provide the requisite sharp filtering but are too bulky, costly, and inflexible to satisfy the needs of SDR and CR. Integrated filters that meet the associated sharpness, linearity, and programmability requirements using existing filtering techniques are either impossible or prohibitive in terms of power, area, and/or cost.

We have developed a new technique called "Filtering by Aliasing" that incorporates the deterministic aliasing effect of the sampling operation into the anti-aliasing function itself. With this technique, sharp, programmable integrated filters can be designed using linear periodically time varying (LPTV) circuits. The proposed LPTV approach dynamically varies the parameters of a simple circuit in a periodic, digitally controlled manner, whose output is finally sampled at the same periodic rate. The LPTV circuit effectively appears as a sharp linear time-invariant (LTI) filter from the continuous-time input to the final sampled output of concern.


[1] S. Hameed and S. Pamarti , "A time-interleaved filtering-by-aliasing receiver front-end achieving >70dB suppression at <4xBandwidth frequency offset", Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2017 IEEE International , pp.418,419, 5-9 Feb. 2017

[2] Hameed, Sameed; Pamarti, Sudhakar, "Design and Analysis of a Programmable Receiver Front End With Time-Interleaved Baseband Analog-FIR Filtering," Solid-State Circuits, IEEE Journal of , vol.53, no.11, pp.3197-3207, Nov. 2018.

[3] Sinha, N.; Rachid, M.; Pavan, S.; Pamarti, S., "Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components," Solid-State Circuits, IEEE Journal of , vol.52, no.8, pp.2009-2025, Aug. 2017.